alltest.fit.rpt

EPM1270下的 LED闪烁程序

+-------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                     ;
+--------------------------------------------------------------------------------+----------+
; Name                                                                           ; Value    ;
+--------------------------------------------------------------------------------+----------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff       ;
; Mid Wire Use - Fit Attempt 1                                                   ; 3        ;
; Mid Slack - Fit Attempt 1                                                      ; -14203   ;
; Internal Atom Count - Fit Attempt 1                                            ; 67       ;
; LE/ALM Count - Fit Attempt 1                                                   ; 67       ;
; LAB Count - Fit Attempt 1                                                      ; 13       ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.385    ;
; Inputs per LAB - Fit Attempt 1                                                 ; 5.077    ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.692    ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:13     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:13     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:13     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:13     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2;1:11 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2;1:11 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:13     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:13     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:13     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2;2:11 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2;1:11 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:13     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2;1:11 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:10;1:3 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:7;1:6  ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:9;1:4  ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:13     ;
; LEs in Chains - Fit Attempt 1                                                  ; 32       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 32       ;
; LABs with Chains - Fit Attempt 1                                               ; 4        ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0        ;
; Time - Fit Attempt 1                                                           ; 0        ;
+--------------------------------------------------------------------------------+----------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 1      ;
; Early Slack - Fit Attempt 1         ; -16555 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 2      ;
; Mid Slack - Fit Attempt 1           ; -9198  ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 2      ;
; Late Slack - Fit Attempt 1          ; -9198  ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016  ;
+-------------------------------------+--------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -8195 ;
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Peak Regional Wire - Fit Attempt 1  ; 3     ;
; Mid Slack - Fit Attempt 1           ; -8416 ;
; Late Slack - Fit Attempt 1          ; -8416 ;
; Late Wire Use - Fit Attempt 1       ; 2     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.062 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 15 13:19:12 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off AllTest -c AllTest
Info: Selected device EPM1270T144C5 for design "AllTest"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 8.240 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y7; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[6]'
    Info: 2: + IC(2.010 ns) + CELL(0.978 ns) = 2.988 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~528'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.111 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~530'
    Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.234 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~526'
    Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 3.357 ns; Loc. = LAB_X4_Y7; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~520'
    Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 3.756 ns; Loc. = LAB_X4_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst|Add0~524'
    Info: 7: + IC(0.000 ns) + CELL(0.246 ns) = 4.002 ns; Loc. = LAB_X4_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst|Add0~514'
    Info: 8: + IC(0.000 ns) + CELL(0.246 ns) = 4.248 ns; Loc. = LAB_X5_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst|Add0~506'
    Info: 9: + IC(0.000 ns) + CELL(0.246 ns) = 4.494 ns; Loc. = LAB_X5_Y7; Fanout = 6; COMB Node = 'FLASH_LED:inst|Add0~492'
    Info: 10: + IC(0.000 ns) + CELL(1.234 ns) = 5.728 ns; Loc. = LAB_X6_Y7; Fanout = 1; COMB Node = 'FLASH_LED:inst|Add0~489'
    Info: 11: + IC(1.329 ns) + CELL(1.183 ns) = 8.240 ns; Loc. = LAB_X8_Y7; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[26]'
    Info: Total cell delay = 4.901 ns ( 59.48 % )
    Info: Total interconnect delay = 3.339 ns ( 40.52 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources
    Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Generated suppressed messages file D:/Nailson/MCU/CPLD/AllTest/AllTest.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 167 megabytes of memory during processing
    Info: Processing ended: Thu Jan 15 13:19:14 2009
    Info: Elapsed time: 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/Nailson/MCU/CPLD/AllTest/AllTest.fit.smsg.