alltest.tan.rpt

EPM1270下的 LED闪烁程序

; N/A                                     ; 134.52 MHz ( period = 7.434 ns )                    ; FLASH_LED:inst|cntr[0]  ; FLASH_LED:inst|cntr[0]  ; clk        ; clk      ; None                        ; None                      ; 6.725 ns                ;
; N/A                                     ; 134.59 MHz ( period = 7.430 ns )                    ; FLASH_LED:inst|cntr[17] ; FLASH_LED:inst|cntr[24] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 134.59 MHz ( period = 7.430 ns )                    ; FLASH_LED:inst|cntr[1]  ; FLASH_LED:inst|cntr[24] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 134.68 MHz ( period = 7.425 ns )                    ; FLASH_LED:inst|cntr[12] ; FLASH_LED:inst|cntr[31] ; clk        ; clk      ; None                        ; None                      ; 6.716 ns                ;
; N/A                                     ; 134.68 MHz ( period = 7.425 ns )                    ; FLASH_LED:inst|cntr[4]  ; FLASH_LED:inst|cntr[24] ; clk        ; clk      ; None                        ; None                      ; 6.716 ns                ;
; N/A                                     ; 134.75 MHz ( period = 7.421 ns )                    ; FLASH_LED:inst|cntr[7]  ; FLASH_LED:inst|cntr[28] ; clk        ; clk      ; None                        ; None                      ; 6.712 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                         ;                         ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+-------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                    ; To   ; From Clock ;
+-------+--------------+------------+-------------------------+------+------------+
; N/A   ; None         ; 8.674 ns   ; FLASH_LED:inst|ctrl_out ; LED1 ; clk        ;
+-------+--------------+------------+-------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 15 13:19:17 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off AllTest -c AllTest
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 108.92 MHz between source register "FLASH_LED:inst|cntr[12]" and destination register "FLASH_LED:inst|cntr[16]" (period= 9.181 ns)
    Info: + Longest register to register delay is 8.472 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y7_N7; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[12]'
        Info: 2: + IC(2.443 ns) + CELL(0.747 ns) = 3.190 ns; Loc. = LC_X4_Y7_N6; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~522'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.313 ns; Loc. = LC_X4_Y7_N7; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~516'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.436 ns; Loc. = LC_X4_Y7_N8; Fanout = 2; COMB Node = 'FLASH_LED:inst|Add0~510'
        Info: 5: + IC(0.000 ns) + CELL(0.399 ns) = 3.835 ns; Loc. = LC_X4_Y7_N9; Fanout = 6; COMB Node = 'FLASH_LED:inst|Add0~514'
        Info: 6: + IC(0.000 ns) + CELL(1.234 ns) = 5.069 ns; Loc. = LC_X5_Y7_N0; Fanout = 1; COMB Node = 'FLASH_LED:inst|Add0~511'
        Info: 7: + IC(3.123 ns) + CELL(0.280 ns) = 8.472 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[16]'
        Info: Total cell delay = 2.906 ns ( 34.30 % )
        Info: Total interconnect delay = 5.566 ns ( 65.70 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X2_Y7_N5; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[16]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: - Longest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X2_Y7_N7; Fanout = 4; REG Node = 'FLASH_LED:inst|cntr[12]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "LED1" through register "FLASH_LED:inst|ctrl_out" is 8.674 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; REG Node = 'FLASH_LED:inst|ctrl_out'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.479 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; REG Node = 'FLASH_LED:inst|ctrl_out'
        Info: 2: + IC(2.157 ns) + CELL(2.322 ns) = 4.479 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'LED1'
        Info: Total cell delay = 2.322 ns ( 51.84 % )
        Info: Total interconnect delay = 2.157 ns ( 48.16 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 113 megabytes of memory during process