alltest.map.rpt

EPM1270下的 LED闪烁程序

; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+
; AllTest.bdf                      ; yes             ; User Block Diagram/Schematic File  ; D:/Nailson/MCU/CPLD/AllTest/AllTest.bdf ;
; FLASH_LED.v                      ; yes             ; User Verilog HDL File              ; D:/Nailson/MCU/CPLD/AllTest/FLASH_LED.v ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 75    ;
;     -- Combinational with no register       ; 42    ;
;     -- Register only                        ; 23    ;
;     -- Combinational with a register        ; 10    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 10    ;
;     -- 3 input functions                    ; 10    ;
;     -- 2 input functions                    ; 31    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 44    ;
;     -- arithmetic mode                      ; 31    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 33    ;
;                                             ;       ;
; Total registers                             ; 33    ;
; Total logic cells in carry chains           ; 32    ;
; I/O pins                                    ; 3     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 33    ;
; Total fan-out                               ; 223   ;
; Average fan-out                             ; 2.86  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name     ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; |AllTest                   ; 75 (0)      ; 33           ; 0           ; 0            ; 0       ; 0         ; 0         ; 3    ; 0            ; 42 (0)       ; 23 (0)            ; 10 (0)           ; 32 (0)          ; 0 (0)      ; |AllTest                ; work         ;
;    |FLASH_LED:inst|        ; 75 (75)     ; 33           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 42 (42)      ; 23 (23)           ; 10 (10)          ; 32 (32)         ; 0 (0)      ; |AllTest|FLASH_LED:inst ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 33    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Jan 15 13:19:08 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AllTest -c AllTest
Info: Found 1 design units, including 1 entities, in source file AllTest.bdf
    Info: Found entity 1: AllTest
Info: Found 1 design units, including 1 entities, in source file FLASH_LED.v
    Info: Found entity 1: FLASH_LED
Info: Found 1 design units, including 1 entities, in source file LCD1602.v
    Info: Found entity 1: LCD1602
Info: Elaborating entity "AllTest" for the top level hierarchy
Info: Elaborating entity "FLASH_LED" for hierarchy "FLASH_LED:inst"
Info: Implemented 78 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 75 logic cells
Info: Generated suppressed messages file D:/Nailson/MCU/CPLD/AllTest/AllTest.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Thu Jan 15 13:19:11 2009
    Info: Elapsed time: 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/Nailson/MCU/CPLD/AllTest/AllTest.map.smsg.