clock.rpt

使用VHDL开发的简易数字时钟软件

seclow2  = DFFE( _EQ017, GLOBAL( clk), !(GLOBAL( settime) & !seclset2), !(GLOBAL( settime) &  seclset2),  VCC);
  _EQ017 = !_LC1_A13 & !_LC2_A13 &  seclow2
         # !_LC1_A13 &  _LC2_A13 & !seclow2;

-- Node name is ':43' = 'seclow3' 
-- Equation name is 'seclow3', location is LC3_A13, type is buried.
seclow3  = DFFE( _EQ018, GLOBAL( clk), !(GLOBAL( settime) & !seclset3), !(GLOBAL( settime) &  seclset3),  VCC);
  _EQ018 = !_LC1_A13 & !_LC4_A13 &  seclow3
         # !_LC1_A13 &  _LC4_A13 & !seclow3;

-- Node name is '|LPM_ADD_SUB:365|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B12', type is buried 
!_LC3_B12 = _LC3_B12~NOT;
_LC3_B12~NOT = LCELL( _EQ019);
  _EQ019 = !hourlow1
         # !hourlow0;

-- Node name is '|LPM_ADD_SUB:563|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C12', type is buried 
_LC3_C12 = LCELL( _EQ020);
  _EQ020 =  minlow0 &  minlow1;

-- Node name is '|LPM_ADD_SUB:563|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ021);
  _EQ021 = !minlow1 &  minlow3
         # !minlow0 &  minlow3
         # !minlow2 &  minlow3
         #  minlow0 &  minlow1 &  minlow2 & !minlow3;

-- Node name is '|LPM_ADD_SUB:838|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ022);
  _EQ022 =  seclow0 &  seclow1;

-- Node name is '|LPM_ADD_SUB:838|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A13', type is buried 
_LC4_A13 = LCELL( _EQ023);
  _EQ023 =  seclow0 &  seclow1 &  seclow2;

-- Node name is '~219~1' 
-- Equation name is '~219~1', location is LC8_B3, type is buried.
-- synthesized logic cell 
_LC8_B3  = LCELL( _EQ024);
  _EQ024 =  _LC2_C10 &  minhigh0 & !minhigh1 & !minhigh2;

-- Node name is '~219~2' 
-- Equation name is '~219~2', location is LC3_C9, type is buried.
-- synthesized logic cell 
_LC3_C9  = LCELL( _EQ025);
  _EQ025 =  _LC1_A13 &  _LC5_C12;

-- Node name is '~219~3' 
-- Equation name is '~219~3', location is LC1_B12, type is buried.
-- synthesized logic cell 
_LC1_B12 = LCELL( _EQ026);
  _EQ026 = !_LC2_C9 &  _LC7_B3;

-- Node name is '~219~4' 
-- Equation name is '~219~4', location is LC2_B9, type is buried.
-- synthesized logic cell 
_LC2_B9  = LCELL( _EQ027);
  _EQ027 = !_LC2_C9 &  _LC3_B12 &  _LC7_B3;

-- Node name is '~219~5' 
-- Equation name is '~219~5', location is LC5_B9, type is buried.
-- synthesized logic cell 
_LC5_B9  = LCELL( _EQ028);
  _EQ028 =  hourlow2 & !_LC2_C9 & !_LC4_B9 &  _LC7_B3;

-- Node name is ':219' 
-- Equation name is '_LC1_A13', type is buried 
!_LC1_A13 = _LC1_A13~NOT;
_LC1_A13~NOT = LCELL( _EQ029);
  _EQ029 =  seclow1
         # !seclow3
         #  seclow2
         # !seclow0;

-- Node name is ':235' 
-- Equation name is '_LC5_C12', type is buried 
!_LC5_C12 = _LC5_C12~NOT;
_LC5_C12~NOT = LCELL( _EQ030);
  _EQ030 = !sechigh2
         #  sechigh1
         # !sechigh0;

-- Node name is ':251' 
-- Equation name is '_LC2_C10', type is buried 
!_LC2_C10 = _LC2_C10~NOT;
_LC2_C10~NOT = LCELL( _EQ031);
  _EQ031 = !minlow3
         #  minlow2
         #  minlow1
         # !minlow0;

-- Node name is '~292~1' 
-- Equation name is '~292~1', location is LC4_B12, type is buried.
-- synthesized logic cell 
_LC4_B12 = LCELL( _EQ032);
  _EQ032 =  hourlow0 & !hourlow1;

-- Node name is ':292' 
-- Equation name is '_LC3_B4', type is buried 
!_LC3_B4 = _LC3_B4~NOT;
_LC3_B4~NOT = LCELL( _EQ033);
  _EQ033 = !hourlow3
         #  hourlow2
         #  hourlow1
         # !hourlow0;

-- Node name is '~311~1' 
-- Equation name is '~311~1', location is LC4_B4, type is buried.
-- synthesized logic cell 
_LC4_B4  = LCELL( _EQ034);
  _EQ034 = !hourhigh1
         #  hourhigh0
         #  hourlow2;

-- Node name is '~311~2' 
-- Equation name is '~311~2', location is LC4_B9, type is buried.
-- synthesized logic cell 
!_LC4_B9 = _LC4_B9~NOT;
_LC4_B9~NOT = LCELL( _EQ035);
  _EQ035 = !hourlow3 &  _LC3_B12;

-- Node name is '~501~1' 
-- Equation name is '~501~1', location is LC7_B3, type is buried.
-- synthesized logic cell 
_LC7_B3  = LCELL( _EQ036);
  _EQ036 =  _LC2_B4 &  minhigh0 & !minhigh1 &  minhigh2;

-- Node name is '~513~1' 
-- Equation name is '~513~1', location is LC2_B4, type is buried.
-- synthesized logic cell 
_LC2_B4  = LCELL( _EQ037);
  _EQ037 =  hourlow3 & !_LC3_B4
         # !_LC3_B4 & !_LC3_B12
         # !_LC3_B4 &  _LC4_B4;

-- Node name is ':609' 
-- Equation name is '_LC1_B3', type is buried 
_LC1_B3  = LCELL( _EQ038);
  _EQ038 =  _LC2_C10 &  minhigh0 &  minhigh1 & !minhigh2
         # !minhigh0 &  minhigh2
         # !_LC2_C10 &  minhigh2;

-- Node name is '~610~1' 
-- Equation name is '~610~1', location is LC2_B3, type is buried.
-- synthesized logic cell 
_LC2_B3  = LCELL( _EQ039);
  _EQ039 =  _LC2_C10 & !minhigh2
         #  _LC2_C10 &  minhigh1
         #  _LC2_C10 & !minhigh0;

-- Node name is ':726' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ040);
  _EQ040 = !_LC2_C10 &  _LC5_C12 &  _LC7_C10
         # !_LC5_C12 &  minlow3;

-- Node name is ':732' 
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ041);
  _EQ041 = !_LC2_C10 & !_LC3_C12 &  minlow2
         # !_LC2_C10 &  _LC3_C12 &  _LC5_C12 & !minlow2
         # !_LC5_C12 &  minlow2;

-- Node name is ':738' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ042);
  _EQ042 = !_LC2_C10 & !minlow0 &  minlow1
         # !_LC2_C10 &  _LC5_C12 &  minlow0 & !minlow1
         # !_LC5_C12 &  minlow1;

-- Node name is ':750' 
-- Equation name is '_LC5_C10', type is buried 
_LC5_C10 = LCELL( _EQ043);
  _EQ043 =  _LC1_B3 &  _LC5_C12
         # !_LC5_C12 &  minhigh2;

-- Node name is ':884' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = LCELL( _EQ044);
  _EQ044 =  _LC1_A13 &  sechigh0 &  sechigh1 & !sechigh2
         # !sechigh0 &  sechigh2
         # !_LC1_A13 &  sechigh2;

-- Node name is ':890' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ045);
  _EQ045 = !_LC1_A13 &  sechigh1
         # !_LC5_C12 & !sechigh0 &  sechigh1
         #  _LC1_A13 & !_LC5_C12 &  sechigh0 & !sechigh1;

-- Node name is '~932~1' 
-- Equation name is '~932~1', location is LC6_B3, type is buried.
-- synthesized logic cell 
_LC6_B3  = LCELL( _EQ046);
  _EQ046 =  _LC2_B3 & !minhigh0 &  minhigh1
         #  _LC2_C9 &  minhigh1;

-- Node name is '~938~1' 
-- Equation name is '~938~1', location is LC2_C9, type is buried.
-- synthesized logic cell 
!_LC2_C9 = _LC2_C9~NOT;
_LC2_C9~NOT = LCELL( _EQ047);
  _EQ047 =  _LC1_A13 &  _LC2_C10 &  _LC5_C12;

-- Node name is '~944~1' 
-- Equation name is '~944~1', location is LC6_B9, type is buried.
-- synthesized logic cell 
_LC6_B9  = LCELL( _EQ048);
  _EQ048 = !hourlow2 &  _LC7_B3
         # !_LC3_B12 &  _LC7_B3
         #  _LC3_B3;

-- Node name is '~950~1' 
-- Equation name is '~950~1', location is LC3_B9, type is buried.
-- synthesized logic cell 
_LC3_B9  = LCELL( _EQ049);
  _EQ049 = !_LC3_B12 &  _LC7_B3
         #  _LC3_B3;

-- Node name is '~956~1' 
-- Equation name is '~956~1', location is LC5_B12, type is buried.
-- synthesized logic cell 
_LC5_B12 = LCELL( _EQ050);
  _EQ050 = !hourlow0 &  hourlow1 &  _LC7_B3
         #  hourlow1 &  _LC3_B3;

-- Node name is '~962~1' 
-- Equation name is '~962~1', location is LC3_B3, type is buried.
-- synthesized logic cell 
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = LCELL( _EQ051);
  _EQ051 = !_LC2_C9 &  minhigh0 & !minhigh1 &  minhigh2;

-- Node name is '~968~1' 
-- Equation name is '~968~1', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ052);
  _EQ052 = !hourhigh0 &  _LC3_B4
         #  _LC2_B4
         #  _LC3_B3;



Project Information                           e:\learning\vhdl\clock\clock.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,892K