📄 clock.rpt
字号:
- 3 - A 13 DFFE + 1 2 1 1 seclow3 (:43)
- 7 - A 13 DFFE + 1 2 1 2 seclow2 (:44)
- 5 - A 13 DFFE + 1 2 1 3 seclow1 (:45)
- 8 - A 13 DFFE + 1 0 1 4 seclow0 (:46)
- 8 - C 12 DFFE + 1 1 1 2 sechigh2 (:47)
- 6 - C 12 DFFE + 1 1 1 3 sechigh1 (:48)
- 1 - C 12 DFFE + 1 1 1 3 sechigh0 (:49)
- 1 - C 09 DFFE + 1 2 1 3 minlow3 (:50)
- 6 - C 10 DFFE + 1 2 1 3 minlow2 (:51)
- 8 - C 10 DFFE + 1 2 1 4 minlow1 (:52)
- 2 - C 12 DFFE + 1 2 1 4 minlow0 (:53)
- 4 - C 10 DFFE + 1 2 1 6 minhigh2 (:54)
- 5 - B 03 DFFE + 1 3 1 6 minhigh1 (:55)
- 4 - B 03 DFFE + 1 1 1 6 minhigh0 (:56)
- 8 - B 09 DFFE + 1 2 1 3 hourlow3 (:57)
- 1 - B 09 DFFE + 1 2 1 4 hourlow2 (:58)
- 2 - B 12 DFFE + 1 3 1 4 hourlow1 (:59)
- 6 - B 12 DFFE + 1 1 1 4 hourlow0 (:60)
- 6 - B 04 AND2 s 0 4 0 1 hourhigh1~1 (~61~1)
- 8 - B 04 DFFE + 1 2 1 2 hourhigh1 (:61)
- 1 - B 04 DFFE + 1 2 1 3 hourhigh0 (:62)
- 8 - B 03 AND2 s 0 4 0 1 ~219~1
- 3 - C 09 AND2 s 0 2 0 1 ~219~2
- 1 - B 12 AND2 s 0 2 0 1 ~219~3
- 2 - B 09 AND2 s 0 3 0 1 ~219~4
- 5 - B 09 AND2 s 0 4 0 1 ~219~5
- 1 - A 13 OR2 ! 0 4 0 13 :219
- 5 - C 12 OR2 ! 0 3 0 8 :235
- 2 - C 10 OR2 ! 0 4 0 7 :251
- 4 - B 12 AND2 s 0 2 0 1 ~292~1
- 3 - B 04 OR2 ! 0 4 0 4 :292
- 4 - B 04 OR2 s 0 3 0 1 ~311~1
- 4 - B 09 AND2 s ! 0 2 0 1 ~311~2
- 7 - B 03 AND2 s 0 4 0 6 ~501~1
- 2 - B 04 OR2 s 0 4 0 2 ~513~1
- 1 - B 03 OR2 0 4 0 1 :609
- 2 - B 03 OR2 s 0 4 0 1 ~610~1
- 4 - C 09 OR2 0 4 0 1 :726
- 3 - C 10 OR2 0 4 0 1 :732
- 1 - C 10 OR2 0 4 0 1 :738
- 5 - C 10 OR2 0 3 0 1 :750
- 7 - C 12 OR2 0 4 0 1 :884
- 4 - C 12 OR2 0 4 0 1 :890
- 6 - B 03 OR2 s 0 4 0 1 ~932~1
- 2 - C 09 AND2 s ! 0 3 0 6 ~938~1
- 6 - B 09 OR2 s 0 4 0 1 ~944~1
- 3 - B 09 OR2 s 0 3 0 1 ~950~1
- 5 - B 12 OR2 s 0 4 0 1 ~956~1
- 3 - B 03 AND2 s ! 0 4 0 7 ~962~1
- 5 - B 04 OR2 s 0 4 0 1 ~968~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\learning\vhdl\clock\clock.rpt
clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 17/ 96( 17%) 10/ 48( 20%) 0/ 48( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 13/ 96( 13%) 7/ 48( 14%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\learning\vhdl\clock\clock.rpt
clock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk
Device-Specific Information: e:\learning\vhdl\clock\clock.rpt
clock
** EQUATIONS **
clk : INPUT;
hourhset0 : INPUT;
hourhset1 : INPUT;
hourlset0 : INPUT;
hourlset1 : INPUT;
hourlset2 : INPUT;
hourlset3 : INPUT;
minhset0 : INPUT;
minhset1 : INPUT;
minhset2 : INPUT;
minlset0 : INPUT;
minlset1 : INPUT;
minlset2 : INPUT;
minlset3 : INPUT;
sechset0 : INPUT;
sechset1 : INPUT;
sechset2 : INPUT;
seclset0 : INPUT;
seclset1 : INPUT;
seclset2 : INPUT;
seclset3 : INPUT;
settime : INPUT;
-- Node name is 'hourhdis0'
-- Equation name is 'hourhdis0', type is output
hourhdis0 = hourhigh0;
-- Node name is 'hourhdis1'
-- Equation name is 'hourhdis1', type is output
hourhdis1 = hourhigh1;
-- Node name is ':62' = 'hourhigh0'
-- Equation name is 'hourhigh0', location is LC1_B4, type is buried.
hourhigh0 = DFFE( _EQ001, GLOBAL( clk), !(GLOBAL( settime) & !hourhset0), !(GLOBAL( settime) & hourhset0), VCC);
_EQ001 = hourhigh0 & !_LC3_B4
# hourhigh0 & _LC3_B3
# !hourhigh0 & !_LC3_B3 & _LC3_B4;
-- Node name is '~61~1' = 'hourhigh1~1'
-- Equation name is '~61~1', location is LC6_B4, type is buried.
-- synthesized logic cell
_LC6_B4 = LCELL( _EQ002);
_EQ002 = hourhigh0 & !hourhigh1 & !_LC3_B3 & _LC3_B4;
-- Node name is ':61' = 'hourhigh1'
-- Equation name is 'hourhigh1', location is LC8_B4, type is buried.
hourhigh1 = DFFE( _EQ003, GLOBAL( clk), !(GLOBAL( settime) & !hourhset1), !(GLOBAL( settime) & hourhset1), VCC);
_EQ003 = hourhigh1 & _LC5_B4
# _LC6_B4;
-- Node name is 'hourldis0'
-- Equation name is 'hourldis0', type is output
hourldis0 = hourlow0;
-- Node name is 'hourldis1'
-- Equation name is 'hourldis1', type is output
hourldis1 = hourlow1;
-- Node name is 'hourldis2'
-- Equation name is 'hourldis2', type is output
hourldis2 = hourlow2;
-- Node name is 'hourldis3'
-- Equation name is 'hourldis3', type is output
hourldis3 = hourlow3;
-- Node name is ':60' = 'hourlow0'
-- Equation name is 'hourlow0', location is LC6_B12, type is buried.
hourlow0 = DFFE( _EQ004, GLOBAL( clk), !(GLOBAL( settime) & !hourlset0), !(GLOBAL( settime) & hourlset0), VCC);
_EQ004 = hourlow0 & _LC3_B3
# !hourlow0 & !_LC3_B3;
-- Node name is ':59' = 'hourlow1'
-- Equation name is 'hourlow1', location is LC2_B12, type is buried.
hourlow1 = DFFE( _EQ005, GLOBAL( clk), !(GLOBAL( settime) & !hourlset1), !(GLOBAL( settime) & hourlset1), VCC);
_EQ005 = _LC1_B12 & _LC4_B12
# _LC5_B12;
-- Node name is ':58' = 'hourlow2'
-- Equation name is 'hourlow2', location is LC1_B9, type is buried.
hourlow2 = DFFE( _EQ006, GLOBAL( clk), !(GLOBAL( settime) & !hourlset2), !(GLOBAL( settime) & hourlset2), VCC);
_EQ006 = !hourlow2 & _LC2_B9
# hourlow2 & _LC3_B9;
-- Node name is ':57' = 'hourlow3'
-- Equation name is 'hourlow3', location is LC8_B9, type is buried.
hourlow3 = DFFE( _EQ007, GLOBAL( clk), !(GLOBAL( settime) & !hourlset3), !(GLOBAL( settime) & hourlset3), VCC);
_EQ007 = _LC5_B9
# hourlow3 & _LC6_B9;
-- Node name is 'minhdis0'
-- Equation name is 'minhdis0', type is output
minhdis0 = minhigh0;
-- Node name is 'minhdis1'
-- Equation name is 'minhdis1', type is output
minhdis1 = minhigh1;
-- Node name is 'minhdis2'
-- Equation name is 'minhdis2', type is output
minhdis2 = minhigh2;
-- Node name is ':56' = 'minhigh0'
-- Equation name is 'minhigh0', location is LC4_B3, type is buried.
minhigh0 = DFFE( _EQ008, GLOBAL( clk), !(GLOBAL( settime) & !minhset0), !(GLOBAL( settime) & minhset0), VCC);
_EQ008 = _LC2_C9 & minhigh0
# !_LC2_C9 & !minhigh0;
-- Node name is ':55' = 'minhigh1'
-- Equation name is 'minhigh1', location is LC5_B3, type is buried.
minhigh1 = DFFE( _EQ009, GLOBAL( clk), !(GLOBAL( settime) & !minhset1), !(GLOBAL( settime) & minhset1), VCC);
_EQ009 = _LC6_B3
# _LC3_C9 & _LC8_B3;
-- Node name is ':54' = 'minhigh2'
-- Equation name is 'minhigh2', location is LC4_C10, type is buried.
minhigh2 = DFFE( _EQ010, GLOBAL( clk), !(GLOBAL( settime) & !minhset2), !(GLOBAL( settime) & minhset2), VCC);
_EQ010 = _LC1_A13 & _LC5_C10
# !_LC1_A13 & minhigh2;
-- Node name is 'minldis0'
-- Equation name is 'minldis0', type is output
minldis0 = minlow0;
-- Node name is 'minldis1'
-- Equation name is 'minldis1', type is output
minldis1 = minlow1;
-- Node name is 'minldis2'
-- Equation name is 'minldis2', type is output
minldis2 = minlow2;
-- Node name is 'minldis3'
-- Equation name is 'minldis3', type is output
minldis3 = minlow3;
-- Node name is ':53' = 'minlow0'
-- Equation name is 'minlow0', location is LC2_C12, type is buried.
minlow0 = DFFE( _EQ011, GLOBAL( clk), !(GLOBAL( settime) & !minlset0), !(GLOBAL( settime) & minlset0), VCC);
_EQ011 = !_LC5_C12 & minlow0
# _LC1_A13 & _LC5_C12 & !minlow0
# !_LC1_A13 & minlow0;
-- Node name is ':52' = 'minlow1'
-- Equation name is 'minlow1', location is LC8_C10, type is buried.
minlow1 = DFFE( _EQ012, GLOBAL( clk), !(GLOBAL( settime) & !minlset1), !(GLOBAL( settime) & minlset1), VCC);
_EQ012 = _LC1_A13 & _LC1_C10
# !_LC1_A13 & minlow1;
-- Node name is ':51' = 'minlow2'
-- Equation name is 'minlow2', location is LC6_C10, type is buried.
minlow2 = DFFE( _EQ013, GLOBAL( clk), !(GLOBAL( settime) & !minlset2), !(GLOBAL( settime) & minlset2), VCC);
_EQ013 = _LC1_A13 & _LC3_C10
# !_LC1_A13 & minlow2;
-- Node name is ':50' = 'minlow3'
-- Equation name is 'minlow3', location is LC1_C9, type is buried.
minlow3 = DFFE( _EQ014, GLOBAL( clk), !(GLOBAL( settime) & !minlset3), !(GLOBAL( settime) & minlset3), VCC);
_EQ014 = _LC1_A13 & _LC4_C9
# !_LC1_A13 & minlow3;
-- Node name is 'sechdis0'
-- Equation name is 'sechdis0', type is output
sechdis0 = sechigh0;
-- Node name is 'sechdis1'
-- Equation name is 'sechdis1', type is output
sechdis1 = sechigh1;
-- Node name is 'sechdis2'
-- Equation name is 'sechdis2', type is output
sechdis2 = sechigh2;
-- Node name is ':49' = 'sechigh0'
-- Equation name is 'sechigh0', location is LC1_C12, type is buried.
sechigh0 = DFFE( _EQ015, GLOBAL( clk), !(GLOBAL( settime) & !sechset0), !(GLOBAL( settime) & sechset0), VCC);
_EQ015 = !_LC1_A13 & sechigh0
# _LC1_A13 & !sechigh0;
-- Node name is ':48' = 'sechigh1'
-- Equation name is 'sechigh1', location is LC6_C12, type is buried.
sechigh1 = DFFE( _LC4_C12, GLOBAL( clk), !(GLOBAL( settime) & !sechset1), !(GLOBAL( settime) & sechset1), VCC);
-- Node name is ':47' = 'sechigh2'
-- Equation name is 'sechigh2', location is LC8_C12, type is buried.
sechigh2 = DFFE( _LC7_C12, GLOBAL( clk), !(GLOBAL( settime) & !sechset2), !(GLOBAL( settime) & sechset2), VCC);
-- Node name is 'secldis0'
-- Equation name is 'secldis0', type is output
secldis0 = seclow0;
-- Node name is 'secldis1'
-- Equation name is 'secldis1', type is output
secldis1 = seclow1;
-- Node name is 'secldis2'
-- Equation name is 'secldis2', type is output
secldis2 = seclow2;
-- Node name is 'secldis3'
-- Equation name is 'secldis3', type is output
secldis3 = seclow3;
-- Node name is ':46' = 'seclow0'
-- Equation name is 'seclow0', location is LC8_A13, type is buried.
seclow0 = DFFE(!seclow0, GLOBAL( clk), !(GLOBAL( settime) & !seclset0), !(GLOBAL( settime) & seclset0), VCC);
-- Node name is ':45' = 'seclow1'
-- Equation name is 'seclow1', location is LC5_A13, type is buried.
seclow1 = DFFE( _EQ016, GLOBAL( clk), !(GLOBAL( settime) & !seclset1), !(GLOBAL( settime) & seclset1), VCC);
_EQ016 = !_LC1_A13 & !seclow0 & seclow1
# !_LC1_A13 & seclow0 & !seclow1;
-- Node name is ':44' = 'seclow2'
-- Equation name is 'seclow2', location is LC7_A13, type is buried.
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