⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 display.rpt

📁 使用VHDL开发的简易数字时钟软件
💻 RPT
📖 第 1 页 / 共 4 页
字号:
_LC3_A1  = LCELL( _EQ061);
  _EQ061 = !_LC3_A23 &  _LC8_A1
         # !hourhdis0 & !hourhdis1 &  _LC3_A23;

-- Node name is '~3868~1' 
-- Equation name is '~3868~1', location is LC7_A5, type is buried.
-- synthesized logic cell 
_LC7_A5  = LCELL( _EQ062);
  _EQ062 = !secldis0 & !secldis1 & !secldis2 &  secldis3
         # !secldis0 &  secldis1 &  secldis2 & !secldis3;

-- Node name is '~3868~2' 
-- Equation name is '~3868~2', location is LC3_A5, type is buried.
-- synthesized logic cell 
_LC3_A5  = LCELL( _EQ063);
  _EQ063 = !_LC4_A5 &  _LC7_A5
         #  _LC1_A5 & !_LC4_A5
         #  _LC8_A5;

-- Node name is '~3868~3' 
-- Equation name is '~3868~3', location is LC4_A8, type is buried.
-- synthesized logic cell 
_LC4_A8  = LCELL( _EQ064);
  _EQ064 = !sechdis0 &  sechdis1;

-- Node name is '~3868~4' 
-- Equation name is '~3868~4', location is LC6_A8, type is buried.
-- synthesized logic cell 
_LC6_A8  = LCELL( _EQ065);
  _EQ065 =  _LC3_A5 & !_LC7_A23
         #  _LC4_A8 &  _LC7_A23
         #  _LC3_A8 &  _LC7_A23;

-- Node name is '~3868~5' 
-- Equation name is '~3868~5', location is LC1_A4, type is buried.
-- synthesized logic cell 
_LC1_A4  = LCELL( _EQ066);
  _EQ066 = !minldis0 & !minldis1 & !minldis2 &  minldis3
         # !minldis0 &  minldis1 &  minldis2 & !minldis3;

-- Node name is '~3868~6' 
-- Equation name is '~3868~6', location is LC3_A4, type is buried.
-- synthesized logic cell 
_LC3_A4  = LCELL( _EQ067);
  _EQ067 =  _LC1_A4 & !_LC6_A6
         # !_LC6_A6 &  _LC8_A4
         #  _LC8_A6;

-- Node name is '~3868~7' 
-- Equation name is '~3868~7', location is LC4_A4, type is buried.
-- synthesized logic cell 
_LC4_A4  = LCELL( _EQ068);
  _EQ068 = !_LC2_A23 & !_LC4_A23 &  _LC6_A8
         # !_LC2_A23 &  _LC3_A4 &  _LC4_A23;

-- Node name is '~3868~8' 
-- Equation name is '~3868~8', location is LC2_A10, type is buried.
-- synthesized logic cell 
_LC2_A10 = LCELL( _EQ069);
  _EQ069 =  _LC2_A23 & !minhdis0 & !minhdis2
         #  _LC2_A23 & !minhdis0 &  minhdis1;

-- Node name is '~3868~9' 
-- Equation name is '~3868~9', location is LC3_A9, type is buried.
-- synthesized logic cell 
_LC3_A9  = LCELL( _EQ070);
  _EQ070 = !hourldis0 & !hourldis1 & !hourldis2 &  hourldis3
         # !hourldis0 &  hourldis1 &  hourldis2 & !hourldis3;

-- Node name is '~3868~10' 
-- Equation name is '~3868~10', location is LC1_A12, type is buried.
-- synthesized logic cell 
_LC1_A12 = LCELL( _EQ071);
  _EQ071 =  _LC3_A9 & !_LC8_A12
         #  _LC6_A12 & !_LC8_A12
         #  _LC5_A9;

-- Node name is '~3868~11' 
-- Equation name is '~3868~11', location is LC5_A4, type is buried.
-- synthesized logic cell 
_LC5_A4  = LCELL( _EQ072);
  _EQ072 = !_LC1_A23 &  _LC4_A4
         # !_LC1_A23 &  _LC2_A10
         #  _LC1_A12 &  _LC1_A23;

-- Node name is ':3868' 
-- Equation name is '_LC7_A4', type is buried 
_LC7_A4  = LCELL( _EQ073);
  _EQ073 = !_LC3_A23 &  _LC5_A4
         # !hourhdis0 &  _LC3_A23;

-- Node name is ':3874' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ074);
  _EQ074 =  _LC1_A7 & !_LC7_A23
         # !_LC7_A23 &  _LC8_A5
         #  _LC2_A8 &  _LC7_A23;

-- Node name is ':3881' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ075);
  _EQ075 =  _LC2_A23 & !minhdis0 &  minhdis1
         #  _LC2_A23 &  minhdis1 & !minhdis2
         #  _LC2_A23 & !minhdis0 & !minhdis2
         #  _LC2_A23 &  minhdis0 & !minhdis1 &  minhdis2;

-- Node name is ':3882' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ076);
  _EQ076 =  _LC1_A6 & !_LC2_A23 &  _LC4_A23
         #  _LC2_A3 & !_LC2_A23 & !_LC4_A23;

-- Node name is ':3883' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ077);
  _EQ077 =  _LC1_A3 & !_LC1_A23
         # !_LC1_A23 &  _LC5_A1
         #  _LC1_A23 &  _LC3_A12;

-- Node name is ':3886' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ078);
  _EQ078 = !_LC3_A23 &  _LC6_A1
         # !hourhdis0 &  _LC3_A23
         #  hourhdis1 &  _LC3_A23;

-- Node name is ':3892' 
-- Equation name is '_LC4_A12', type is buried 
_LC4_A12 = LCELL( _EQ079);
  _EQ079 = !_LC1_A5 & !_LC7_A23
         # !_LC5_A8 &  _LC7_A23;

-- Node name is ':3899' 
-- Equation name is '_LC4_A10', type is buried 
_LC4_A10 = LCELL( _EQ080);
  _EQ080 =  _LC2_A23 & !minhdis1
         #  _LC2_A23 &  minhdis0
         #  _LC2_A23 &  minhdis2;

-- Node name is ':3900' 
-- Equation name is '_LC5_A12', type is buried 
_LC5_A12 = LCELL( _EQ081);
  _EQ081 = !_LC2_A23 &  _LC4_A23 & !_LC8_A4
         # !_LC2_A23 &  _LC4_A12 & !_LC4_A23;

-- Node name is ':3901' 
-- Equation name is '_LC7_A12', type is buried 
_LC7_A12 = LCELL( _EQ082);
  _EQ082 = !_LC1_A23 &  _LC5_A12
         # !_LC1_A23 &  _LC4_A10
         #  _LC1_A23 & !_LC6_A12;

-- Node name is ':3904' 
-- Equation name is '_LC2_A12', type is buried 
_LC2_A12 = LCELL( _EQ083);
  _EQ083 = !_LC3_A23 &  _LC7_A12
         # !hourhdis1 &  _LC3_A23
         #  hourhdis0 &  _LC3_A23;

-- Node name is ':3910' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ084);
  _EQ084 =  _LC7_A11 & !_LC7_A23
         #  _LC7_A23 &  _LC8_A11
         #  _LC3_A8 &  _LC7_A23;

-- Node name is ':3917' 
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = LCELL( _EQ085);
  _EQ085 =  _LC2_A23 & !minhdis2
         #  _LC2_A23 &  minhdis0 &  minhdis1
         #  _LC2_A23 & !minhdis0 & !minhdis1;

-- Node name is ':3918' 
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = LCELL( _EQ086);
  _EQ086 = !_LC2_A23 &  _LC4_A6 &  _LC4_A23
         #  _LC1_A11 & !_LC2_A23 & !_LC4_A23;

-- Node name is ':3919' 
-- Equation name is '_LC7_A10', type is buried 
_LC7_A10 = LCELL( _EQ087);
  _EQ087 =  _LC1_A10 & !_LC1_A23
         # !_LC1_A23 &  _LC3_A10
         #  _LC1_A23 &  _LC6_A10;

-- Node name is ':3922' 
-- Equation name is '_LC5_A10', type is buried 
_LC5_A10 = LCELL( _EQ088);
  _EQ088 =  _LC7_A10
         #  _LC3_A23;

-- Node name is ':3928' 
-- Equation name is '_LC6_A11', type is buried 
_LC6_A11 = LCELL( _EQ089);
  _EQ089 = !_LC7_A23 &  _LC8_A5
         #  _LC2_A11 & !_LC7_A23
         #  _LC3_A11 &  _LC7_A23;

-- Node name is ':3931' 
-- Equation name is '_LC5_A11', type is buried 
_LC5_A11 = LCELL( _EQ090);
  _EQ090 =  _LC4_A23 &  _LC8_A6
         #  _LC2_A6 &  _LC4_A23
         # !_LC4_A23 &  _LC6_A11;

-- Node name is ':3934' 
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ091);
  _EQ091 = !_LC2_A23 &  _LC5_A11
         #  _LC2_A23 &  _LC5_A22
         #  _LC2_A23 &  _LC6_A22;

-- Node name is ':3937' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ092);
  _EQ092 = !_LC1_A23 &  _LC7_A22
         #  _LC1_A23 &  _LC5_A9
         #  _LC1_A23 &  _LC4_A9;

-- Node name is ':3940' 
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = LCELL( _EQ093);
  _EQ093 = !_LC3_A23 &  _LC8_A22
         # !hourhdis0 &  _LC3_A23
         #  hourhdis1 &  _LC3_A23;

-- Node name is ':3994' 
-- Equation name is '_LC3_A22', type is buried 
_LC3_A22 = LCELL( _EQ094);
  _EQ094 = !_LC1_A23 &  _LC2_A23
         # !_LC1_A23 &  _LC7_A23
         #  _LC3_A23;



Project Information                         e:\learning\vhdl\clock\display.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,613K

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -