📄 display.rpt
字号:
- 5 - A 07 OR2 0 3 0 1 :3483
- 5 - A 05 OR2 4 0 0 1 :3536
- 1 - A 07 OR2 0 3 0 1 :3545
- 6 - A 05 OR2 4 0 0 1 :3593
- 4 - A 11 AND2 s 3 0 0 3 ~3603~1
- 7 - A 11 OR2 0 4 0 1 :3603
- 2 - A 11 OR2 4 0 0 2 :3635
- 7 - A 23 AND2 0 3 1 10 :3663
- 4 - A 23 AND2 0 3 1 9 :3673
- 2 - A 23 AND2 0 3 1 16 :3683
- 1 - A 23 OR2 ! 0 3 1 10 :3693
- 3 - A 23 AND2 0 3 1 10 :3703
- 4 - A 01 AND2 s ! 0 3 0 2 ~3706~1
- 5 - A 23 OR2 0 3 1 0 :3706
- 4 - A 03 OR2 0 4 0 1 :3820
- 1 - A 08 OR2 s 3 0 0 1 ~3821~1
- 2 - A 05 OR2 s 4 0 0 2 ~3822~1
- 3 - A 03 OR2 s 4 0 0 1 ~3824~1
- 2 - A 01 OR2 3 1 0 1 :3827
- 6 - A 03 OR2 0 4 0 1 :3828
- 7 - A 03 OR2 0 4 0 1 :3829
- 2 - A 09 OR2 s 4 0 0 1 ~3830~1
- 5 - A 03 OR2 1 2 1 0 :3832
- 8 - A 08 OR2 0 4 0 1 :3838
- 7 - A 01 OR2 3 1 0 1 :3845
- 2 - A 04 OR2 0 4 0 1 :3846
- 8 - A 01 OR2 0 4 0 1 :3847
- 3 - A 01 OR2 2 2 1 0 :3850
- 7 - A 05 OR2 s 4 0 0 1 ~3868~1
- 3 - A 05 OR2 s 0 4 0 1 ~3868~2
- 4 - A 08 AND2 s 2 0 0 1 ~3868~3
- 6 - A 08 OR2 s 0 4 0 1 ~3868~4
- 1 - A 04 OR2 s 4 0 0 1 ~3868~5
- 3 - A 04 OR2 s 0 4 0 1 ~3868~6
- 4 - A 04 OR2 s 0 4 0 1 ~3868~7
- 2 - A 10 OR2 s 3 1 0 1 ~3868~8
- 3 - A 09 OR2 s 4 0 0 1 ~3868~9
- 1 - A 12 OR2 s 0 4 0 1 ~3868~10
- 5 - A 04 OR2 s 0 4 0 1 ~3868~11
- 7 - A 04 OR2 1 2 1 0 :3868
- 2 - A 03 OR2 0 4 0 1 :3874
- 5 - A 01 OR2 3 1 0 1 :3881
- 1 - A 03 OR2 0 4 0 1 :3882
- 6 - A 01 OR2 0 4 0 1 :3883
- 1 - A 01 OR2 2 2 1 0 :3886
- 4 - A 12 OR2 0 3 0 1 :3892
- 4 - A 10 OR2 3 1 0 1 :3899
- 5 - A 12 OR2 0 4 0 1 :3900
- 7 - A 12 OR2 0 4 0 1 :3901
- 2 - A 12 OR2 2 2 1 0 :3904
- 1 - A 11 OR2 0 4 0 1 :3910
- 3 - A 10 OR2 3 1 0 1 :3917
- 1 - A 10 OR2 0 4 0 1 :3918
- 7 - A 10 OR2 0 4 0 1 :3919
- 5 - A 10 OR2 0 2 1 0 :3922
- 6 - A 11 OR2 0 4 0 1 :3928
- 5 - A 11 OR2 0 4 0 1 :3931
- 7 - A 22 OR2 0 4 0 1 :3934
- 8 - A 22 OR2 0 4 0 1 :3937
- 4 - A 22 OR2 2 2 1 0 :3940
- 3 - A 22 OR2 0 4 0 1 :3994
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\learning\vhdl\clock\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 36/ 96( 37%) 28/ 48( 58%) 4/ 48( 8%) 4/16( 25%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\learning\vhdl\clock\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 SCLK
Device-Specific Information: e:\learning\vhdl\clock\display.rpt
display
** EQUATIONS **
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
SCLK : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ADDSEL0'
-- Equation name is 'ADDSEL0', type is output
ADDSEL0 = !_LC3_A23;
-- Node name is 'ADDSEL1'
-- Equation name is 'ADDSEL1', type is output
ADDSEL1 = !_LC1_A23;
-- Node name is 'ADDSEL2'
-- Equation name is 'ADDSEL2', type is output
ADDSEL2 = !_LC2_A23;
-- Node name is 'ADDSEL3'
-- Equation name is 'ADDSEL3', type is output
ADDSEL3 = !_LC4_A23;
-- Node name is 'ADDSEL4'
-- Equation name is 'ADDSEL4', type is output
ADDSEL4 = !_LC7_A23;
-- Node name is 'ADDSEL5'
-- Equation name is 'ADDSEL5', type is output
ADDSEL5 = _LC5_A23;
-- Node name is ':42' = 'CURSTA0'
-- Equation name is 'CURSTA0', location is LC2_A22, type is buried.
CURSTA0 = DFFE( _LC3_A22, GLOBAL( SCLK), VCC, VCC, !_LC1_A22);
-- Node name is ':41' = 'CURSTA1'
-- Equation name is 'CURSTA1', location is LC6_A23, type is buried.
CURSTA1 = DFFE( _EQ001, GLOBAL( SCLK), VCC, VCC, !_LC1_A22);
_EQ001 = _LC2_A23 & !_LC3_A23
# _LC1_A23 & !_LC3_A23;
-- Node name is ':40' = 'CURSTA2'
-- Equation name is 'CURSTA2', location is LC8_A23, type is buried.
CURSTA2 = DFFE( _EQ002, GLOBAL( SCLK), VCC, VCC, !_LC1_A22);
_EQ002 = !_LC4_A1 & _LC4_A23
# !_LC4_A1 & _LC7_A23;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC1_A22, type is buried.
-- synthesized logic cell
!_LC1_A22 = _LC1_A22~NOT;
_LC1_A22~NOT = LCELL(!RESET);
-- Node name is 'SECDIS0'
-- Equation name is 'SECDIS0', type is output
SECDIS0 = _LC4_A22;
-- Node name is 'SECDIS1'
-- Equation name is 'SECDIS1', type is output
SECDIS1 = _LC5_A10;
-- Node name is 'SECDIS2'
-- Equation name is 'SECDIS2', type is output
SECDIS2 = _LC2_A12;
-- Node name is 'SECDIS3'
-- Equation name is 'SECDIS3', type is output
SECDIS3 = _LC1_A1;
-- Node name is 'SECDIS4'
-- Equation name is 'SECDIS4', type is output
SECDIS4 = _LC7_A4;
-- Node name is 'SECDIS5'
-- Equation name is 'SECDIS5', type is output
SECDIS5 = _LC3_A1;
-- Node name is 'SECDIS6'
-- Equation name is 'SECDIS6', type is output
SECDIS6 = _LC5_A3;
-- Node name is 'SECDIS7'
-- Equation name is 'SECDIS7', type is output
SECDIS7 = GND;
-- Node name is ':1376'
-- Equation name is '_LC6_A12', type is buried
!_LC6_A12 = _LC6_A12~NOT;
_LC6_A12~NOT = LCELL( _EQ003);
_EQ003 = hourldis3
# hourldis0
# !hourldis1
# hourldis2;
-- Node name is ':1388'
-- Equation name is '_LC8_A12', type is buried
!_LC8_A12 = _LC8_A12~NOT;
_LC8_A12~NOT = LCELL( _EQ004);
_EQ004 = hourldis3
# !hourldis0
# hourldis1
# hourldis2;
-- Node name is ':1400'
-- Equation name is '_LC5_A9', type is buried
_LC5_A9 = LCELL( _EQ005);
_EQ005 = !hourldis0 & !hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1463'
-- Equation name is '_LC7_A9', type is buried
_LC7_A9 = LCELL( _EQ006);
_EQ006 = hourldis3
# !hourldis1 & hourldis2
# !hourldis0 & !hourldis1
# !hourldis0 & hourldis2;
-- Node name is ':1516'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ007);
_EQ007 = hourldis3
# !hourldis2
# hourldis0 & !hourldis1
# !hourldis0 & hourldis1;
-- Node name is ':1523'
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ008);
_EQ008 = _LC1_A9 & !_LC8_A12
# _LC6_A9 & !_LC8_A12
# _LC5_A9;
-- Node name is ':1573'
-- Equation name is '_LC8_A9', type is buried
_LC8_A9 = LCELL( _EQ009);
_EQ009 = hourldis3
# !hourldis2
# !hourldis0 & !hourldis1
# hourldis0 & hourldis1;
-- Node name is '~1583~1'
-- Equation name is '~1583~1', location is LC6_A9, type is buried.
-- synthesized logic cell
_LC6_A9 = LCELL( _EQ010);
_EQ010 = hourldis1 & !hourldis2 & !hourldis3;
-- Node name is ':1583'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ011);
_EQ011 = _LC6_A9
# _LC8_A9
# !_LC4_A9
# _LC5_A9;
-- Node name is ':1615'
-- Equation name is '_LC4_A9', type is buried
_LC4_A9 = LCELL( _EQ012);
_EQ012 = hourldis3
# hourldis1
# hourldis0 & hourldis2
# !hourldis0 & !hourldis2;
-- Node name is ':1895'
-- Equation name is '_LC5_A22', type is buried
_LC5_A22 = LCELL( _EQ013);
_EQ013 = !minhdis0 & !minhdis1 & !minhdis2;
-- Node name is ':2110'
-- Equation name is '_LC6_A22', type is buried
_LC6_A22 = LCELL( _EQ014);
_EQ014 = minhdis1
# !minhdis0 & !minhdis2
# minhdis0 & minhdis2;
-- Node name is ':2386'
-- Equation name is '_LC8_A4', type is buried
!_LC8_A4 = _LC8_A4~NOT;
_LC8_A4~NOT = LCELL( _EQ015);
_EQ015 = minldis3
# minldis0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -