ram.rpt

使用VHDL开发的简易数字时钟软件

-- Node name is ':19' = 'ram17_3' 
-- Equation name is 'ram17_3', location is LC1_A13, type is buried.
ram17_3  = DFFE( _EQ032, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ032 = !addr0 &  ram17_3
         # !_LC4_A14 &  ram17_3
         #  addr0 &  data_i3 &  _LC4_A14;

-- Node name is ':11' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = DFFE( _EQ033, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ033 = !cs &  _LC4_A16 & !wr
         #  _LC8_A14 &  wr
         #  cs &  _LC8_A14;

-- Node name is ':13' 
-- Equation name is '_LC6_A14', type is buried 
_LC6_A14 = DFFE( _EQ034, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ034 = !cs &  _LC2_A17 & !wr
         #  _LC6_A14 &  wr
         #  cs &  _LC6_A14;

-- Node name is ':15' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = DFFE( _EQ035, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ035 = !cs &  _LC8_A20 & !wr
         #  _LC2_A20 &  wr
         #  cs &  _LC2_A20;

-- Node name is ':17' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = DFFE( _EQ036, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ036 = !cs &  _LC2_A21 & !wr
         #  _LC2_A22 &  wr
         #  cs &  _LC2_A22;

-- Node name is '~1011~1' 
-- Equation name is '~1011~1', location is LC1_A14, type is buried.
-- synthesized logic cell 
_LC1_A14 = LCELL( _EQ037);
  _EQ037 = !addr1 &  addr2 & !cs &  wr;

-- Node name is '~1011~2' 
-- Equation name is '~1011~2', location is LC4_A14, type is buried.
-- synthesized logic cell 
_LC4_A14 = LCELL( _EQ038);
  _EQ038 =  addr1 &  addr2 & !cs &  wr;

-- Node name is '~1494~1' 
-- Equation name is '~1494~1', location is LC5_A14, type is buried.
-- synthesized logic cell 
!_LC5_A14 = _LC5_A14~NOT;
_LC5_A14~NOT = LCELL( _EQ039);
  _EQ039 =  addr1 & !addr2 & !cs &  wr;

-- Node name is '~1542~1' 
-- Equation name is '~1542~1', location is LC3_A14, type is buried.
-- synthesized logic cell 
!_LC3_A14 = _LC3_A14~NOT;
_LC3_A14~NOT = LCELL( _EQ040);
  _EQ040 = !addr1 & !addr2 & !cs &  wr;

-- Node name is '~1548~1' 
-- Equation name is '~1548~1', location is LC6_A16, type is buried.
-- synthesized logic cell 
_LC6_A16 = LCELL( _EQ041);
  _EQ041 = !addr1 & !addr2 &  ram10_3
         # !addr1 &  addr2 &  ram14_3;

-- Node name is '~1548~2' 
-- Equation name is '~1548~2', location is LC7_A16, type is buried.
-- synthesized logic cell 
_LC7_A16 = LCELL( _EQ042);
  _EQ042 =  addr1 & !addr2 &  ram12_3
         #  addr1 &  addr2 &  ram16_3;

-- Node name is '~1548~3' 
-- Equation name is '~1548~3', location is LC2_A24, type is buried.
-- synthesized logic cell 
_LC2_A24 = LCELL( _EQ043);
  _EQ043 = !addr2 &  ram11_3
         #  addr2 &  ram15_3;

-- Node name is '~1548~4' 
-- Equation name is '~1548~4', location is LC2_A14, type is buried.
-- synthesized logic cell 
_LC2_A14 = LCELL( _EQ044);
  _EQ044 = !addr2 &  ram13_3
         #  addr2 &  ram17_3;

-- Node name is '~1548~5' 
-- Equation name is '~1548~5', location is LC8_A16, type is buried.
-- synthesized logic cell 
_LC8_A16 = LCELL( _EQ045);
  _EQ045 = !addr1 &  _LC2_A24
         #  addr1 &  _LC2_A14;

-- Node name is '~1548~6' 
-- Equation name is '~1548~6', location is LC4_A16, type is buried.
-- synthesized logic cell 
_LC4_A16 = LCELL( _EQ046);
  _EQ046 = !addr0 &  _LC6_A16
         # !addr0 &  _LC7_A16
         #  addr0 &  _LC8_A16;

-- Node name is '~1554~1' 
-- Equation name is '~1554~1', location is LC6_A17, type is buried.
-- synthesized logic cell 
_LC6_A17 = LCELL( _EQ047);
  _EQ047 = !addr1 & !addr2 &  ram10_2
         # !addr1 &  addr2 &  ram14_2;

-- Node name is '~1554~2' 
-- Equation name is '~1554~2', location is LC5_A19, type is buried.
-- synthesized logic cell 
_LC5_A19 = LCELL( _EQ048);
  _EQ048 =  addr1 & !addr2 &  ram12_2
         #  addr1 &  addr2 &  ram16_2;

-- Node name is '~1554~3' 
-- Equation name is '~1554~3', location is LC7_A17, type is buried.
-- synthesized logic cell 
_LC7_A17 = LCELL( _EQ049);
  _EQ049 = !addr2 &  ram11_2
         #  addr2 &  ram15_2;

-- Node name is '~1554~4' 
-- Equation name is '~1554~4', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ050);
  _EQ050 = !addr2 &  ram13_2
         #  addr2 &  ram17_2;

-- Node name is '~1554~5' 
-- Equation name is '~1554~5', location is LC8_A17, type is buried.
-- synthesized logic cell 
_LC8_A17 = LCELL( _EQ051);
  _EQ051 = !addr1 &  _LC7_A17
         #  addr1 &  _LC2_A19;

-- Node name is '~1554~6' 
-- Equation name is '~1554~6', location is LC2_A17, type is buried.
-- synthesized logic cell 
_LC2_A17 = LCELL( _EQ052);
  _EQ052 = !addr0 &  _LC6_A17
         # !addr0 &  _LC5_A19
         #  addr0 &  _LC8_A17;

-- Node name is '~1560~1' 
-- Equation name is '~1560~1', location is LC1_A18, type is buried.
-- synthesized logic cell 
_LC1_A18 = LCELL( _EQ053);
  _EQ053 = !addr1 & !addr2 &  ram10_1
         # !addr1 &  addr2 &  ram14_1;

-- Node name is '~1560~2' 
-- Equation name is '~1560~2', location is LC5_A20, type is buried.
-- synthesized logic cell 
_LC5_A20 = LCELL( _EQ054);
  _EQ054 =  addr1 & !addr2 &  ram12_1
         #  addr1 &  addr2 &  ram16_1;

-- Node name is '~1560~3' 
-- Equation name is '~1560~3', location is LC6_A20, type is buried.
-- synthesized logic cell 
_LC6_A20 = LCELL( _EQ055);
  _EQ055 = !addr2 &  ram11_1
         #  addr2 &  ram15_1;

-- Node name is '~1560~4' 
-- Equation name is '~1560~4', location is LC8_A18, type is buried.
-- synthesized logic cell 
_LC8_A18 = LCELL( _EQ056);
  _EQ056 = !addr2 &  ram13_1
         #  addr2 &  ram17_1;

-- Node name is '~1560~5' 
-- Equation name is '~1560~5', location is LC7_A20, type is buried.
-- synthesized logic cell 
_LC7_A20 = LCELL( _EQ057);
  _EQ057 = !addr1 &  _LC6_A20
         #  addr1 &  _LC8_A18;

-- Node name is '~1560~6' 
-- Equation name is '~1560~6', location is LC8_A20, type is buried.
-- synthesized logic cell 
_LC8_A20 = LCELL( _EQ058);
  _EQ058 = !addr0 &  _LC1_A18
         # !addr0 &  _LC5_A20
         #  addr0 &  _LC7_A20;

-- Node name is '~1566~1' 
-- Equation name is '~1566~1', location is LC6_A21, type is buried.
-- synthesized logic cell 
_LC6_A21 = LCELL( _EQ059);
  _EQ059 = !addr1 & !addr2 &  ram10_0
         # !addr1 &  addr2 &  ram14_0;

-- Node name is '~1566~2' 
-- Equation name is '~1566~2', location is LC4_A24, type is buried.
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ060);
  _EQ060 =  addr1 & !addr2 &  ram12_0
         #  addr1 &  addr2 &  ram16_0;

-- Node name is '~1566~3' 
-- Equation name is '~1566~3', location is LC8_A24, type is buried.
-- synthesized logic cell 
_LC8_A24 = LCELL( _EQ061);
  _EQ061 = !addr2 &  ram11_0
         #  addr2 &  ram15_0;

-- Node name is '~1566~4' 
-- Equation name is '~1566~4', location is LC7_A21, type is buried.
-- synthesized logic cell 
_LC7_A21 = LCELL( _EQ062);
  _EQ062 = !addr2 &  ram13_0
         #  addr2 &  ram17_0;

-- Node name is '~1566~5' 
-- Equation name is '~1566~5', location is LC8_A21, type is buried.
-- synthesized logic cell 
_LC8_A21 = LCELL( _EQ063);
  _EQ063 = !addr1 &  _LC8_A24
         #  addr1 &  _LC7_A21;

-- Node name is '~1566~6' 
-- Equation name is '~1566~6', location is LC2_A21, type is buried.
-- synthesized logic cell 
_LC2_A21 = LCELL( _EQ064);
  _EQ064 = !addr0 &  _LC6_A21
         # !addr0 &  _LC4_A24
         #  addr0 &  _LC8_A21;



Project Information                             e:\learning\vhdl\clock\ram.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,973K