📄 ram.rpt
字号:
- 7 - A 20 OR2 s 1 2 0 1 ~1560~5
- 8 - A 20 OR2 s 1 3 0 1 ~1560~6
- 6 - A 21 OR2 s 2 2 0 1 ~1566~1
- 4 - A 24 OR2 s 2 2 0 1 ~1566~2
- 8 - A 24 OR2 s 1 2 0 1 ~1566~3
- 7 - A 21 OR2 s 1 2 0 1 ~1566~4
- 8 - A 21 OR2 s 1 2 0 1 ~1566~5
- 2 - A 21 OR2 s 1 3 0 1 ~1566~6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\learning\vhdl\clock\ram.rpt
ram
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 19/ 96( 19%) 0/ 48( 0%) 7/ 48( 14%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\learning\vhdl\clock\ram.rpt
ram
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 36 clk
Device-Specific Information: e:\learning\vhdl\clock\ram.rpt
ram
** EQUATIONS **
addr0 : INPUT;
addr1 : INPUT;
addr2 : INPUT;
clk : INPUT;
cs : INPUT;
data_i0 : INPUT;
data_i1 : INPUT;
data_i2 : INPUT;
data_i3 : INPUT;
wr : INPUT;
-- Node name is 'data_o0'
-- Equation name is 'data_o0', type is output
data_o0 = _LC2_A22;
-- Node name is 'data_o1'
-- Equation name is 'data_o1', type is output
data_o1 = _LC2_A20;
-- Node name is 'data_o2'
-- Equation name is 'data_o2', type is output
data_o2 = _LC6_A14;
-- Node name is 'data_o3'
-- Equation name is 'data_o3', type is output
data_o3 = _LC8_A14;
-- Node name is ':50' = 'ram10_0'
-- Equation name is 'ram10_0', location is LC4_A21, type is buried.
ram10_0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = addr0 & ram10_0
# _LC3_A14 & ram10_0
# !addr0 & data_i0 & !_LC3_A14;
-- Node name is ':49' = 'ram10_1'
-- Equation name is 'ram10_1', location is LC5_A18, type is buried.
ram10_1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = addr0 & ram10_1
# _LC3_A14 & ram10_1
# !addr0 & data_i1 & !_LC3_A14;
-- Node name is ':48' = 'ram10_2'
-- Equation name is 'ram10_2', location is LC4_A17, type is buried.
ram10_2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = addr0 & ram10_2
# _LC3_A14 & ram10_2
# !addr0 & data_i2 & !_LC3_A14;
-- Node name is ':47' = 'ram10_3'
-- Equation name is 'ram10_3', location is LC1_A16, type is buried.
ram10_3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = addr0 & ram10_3
# _LC3_A14 & ram10_3
# !addr0 & data_i3 & !_LC3_A14;
-- Node name is ':46' = 'ram11_0'
-- Equation name is 'ram11_0', location is LC1_A24, type is buried.
ram11_0 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !addr0 & ram11_0
# _LC3_A14 & ram11_0
# addr0 & data_i0 & !_LC3_A14;
-- Node name is ':45' = 'ram11_1'
-- Equation name is 'ram11_1', location is LC1_A20, type is buried.
ram11_1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !addr0 & ram11_1
# _LC3_A14 & ram11_1
# addr0 & data_i1 & !_LC3_A14;
-- Node name is ':44' = 'ram11_2'
-- Equation name is 'ram11_2', location is LC1_A17, type is buried.
ram11_2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !addr0 & ram11_2
# _LC3_A14 & ram11_2
# addr0 & data_i2 & !_LC3_A14;
-- Node name is ':43' = 'ram11_3'
-- Equation name is 'ram11_3', location is LC5_A24, type is buried.
ram11_3 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !addr0 & ram11_3
# _LC3_A14 & ram11_3
# addr0 & data_i3 & !_LC3_A14;
-- Node name is ':42' = 'ram12_0'
-- Equation name is 'ram12_0', location is LC6_A18, type is buried.
ram12_0 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = addr0 & ram12_0
# _LC5_A14 & ram12_0
# !addr0 & data_i0 & !_LC5_A14;
-- Node name is ':41' = 'ram12_1'
-- Equation name is 'ram12_1', location is LC3_A20, type is buried.
ram12_1 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = addr0 & ram12_1
# _LC5_A14 & ram12_1
# !addr0 & data_i1 & !_LC5_A14;
-- Node name is ':40' = 'ram12_2'
-- Equation name is 'ram12_2', location is LC4_A19, type is buried.
ram12_2 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = addr0 & ram12_2
# _LC5_A14 & ram12_2
# !addr0 & data_i2 & !_LC5_A14;
-- Node name is ':39' = 'ram12_3'
-- Equation name is 'ram12_3', location is LC3_A16, type is buried.
ram12_3 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = addr0 & ram12_3
# _LC5_A14 & ram12_3
# !addr0 & data_i3 & !_LC5_A14;
-- Node name is ':38' = 'ram13_0'
-- Equation name is 'ram13_0', location is LC1_A21, type is buried.
ram13_0 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !addr0 & ram13_0
# _LC5_A14 & ram13_0
# addr0 & data_i0 & !_LC5_A14;
-- Node name is ':37' = 'ram13_1'
-- Equation name is 'ram13_1', location is LC2_A18, type is buried.
ram13_1 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !addr0 & ram13_1
# _LC5_A14 & ram13_1
# addr0 & data_i1 & !_LC5_A14;
-- Node name is ':36' = 'ram13_2'
-- Equation name is 'ram13_2', location is LC1_A19, type is buried.
ram13_2 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !addr0 & ram13_2
# _LC5_A14 & ram13_2
# addr0 & data_i2 & !_LC5_A14;
-- Node name is ':35' = 'ram13_3'
-- Equation name is 'ram13_3', location is LC7_A14, type is buried.
ram13_3 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !addr0 & ram13_3
# _LC5_A14 & ram13_3
# addr0 & data_i3 & !_LC5_A14;
-- Node name is ':34' = 'ram14_0'
-- Equation name is 'ram14_0', location is LC5_A21, type is buried.
ram14_0 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = addr0 & ram14_0
# !_LC1_A14 & ram14_0
# !addr0 & data_i0 & _LC1_A14;
-- Node name is ':33' = 'ram14_1'
-- Equation name is 'ram14_1', location is LC7_A18, type is buried.
ram14_1 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = addr0 & ram14_1
# !_LC1_A14 & ram14_1
# !addr0 & data_i1 & _LC1_A14;
-- Node name is ':32' = 'ram14_2'
-- Equation name is 'ram14_2', location is LC5_A17, type is buried.
ram14_2 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = addr0 & ram14_2
# !_LC1_A14 & ram14_2
# !addr0 & data_i2 & _LC1_A14;
-- Node name is ':31' = 'ram14_3'
-- Equation name is 'ram14_3', location is LC2_A16, type is buried.
ram14_3 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = addr0 & ram14_3
# !_LC1_A14 & ram14_3
# !addr0 & data_i3 & _LC1_A14;
-- Node name is ':30' = 'ram15_0'
-- Equation name is 'ram15_0', location is LC3_A24, type is buried.
ram15_0 = DFFE( _EQ021, GLOBAL( clk), VCC, VCC, VCC);
_EQ021 = !addr0 & ram15_0
# !_LC1_A14 & ram15_0
# addr0 & data_i0 & _LC1_A14;
-- Node name is ':29' = 'ram15_1'
-- Equation name is 'ram15_1', location is LC4_A18, type is buried.
ram15_1 = DFFE( _EQ022, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = !addr0 & ram15_1
# !_LC1_A14 & ram15_1
# addr0 & data_i1 & _LC1_A14;
-- Node name is ':28' = 'ram15_2'
-- Equation name is 'ram15_2', location is LC3_A17, type is buried.
ram15_2 = DFFE( _EQ023, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = !addr0 & ram15_2
# !_LC1_A14 & ram15_2
# addr0 & data_i2 & _LC1_A14;
-- Node name is ':27' = 'ram15_3'
-- Equation name is 'ram15_3', location is LC6_A24, type is buried.
ram15_3 = DFFE( _EQ024, GLOBAL( clk), VCC, VCC, VCC);
_EQ024 = !addr0 & ram15_3
# !_LC1_A14 & ram15_3
# addr0 & data_i3 & _LC1_A14;
-- Node name is ':26' = 'ram16_0'
-- Equation name is 'ram16_0', location is LC7_A24, type is buried.
ram16_0 = DFFE( _EQ025, GLOBAL( clk), VCC, VCC, VCC);
_EQ025 = addr0 & ram16_0
# !_LC4_A14 & ram16_0
# !addr0 & data_i0 & _LC4_A14;
-- Node name is ':25' = 'ram16_1'
-- Equation name is 'ram16_1', location is LC4_A20, type is buried.
ram16_1 = DFFE( _EQ026, GLOBAL( clk), VCC, VCC, VCC);
_EQ026 = addr0 & ram16_1
# !_LC4_A14 & ram16_1
# !addr0 & data_i1 & _LC4_A14;
-- Node name is ':24' = 'ram16_2'
-- Equation name is 'ram16_2', location is LC6_A19, type is buried.
ram16_2 = DFFE( _EQ027, GLOBAL( clk), VCC, VCC, VCC);
_EQ027 = addr0 & ram16_2
# !_LC4_A14 & ram16_2
# !addr0 & data_i2 & _LC4_A14;
-- Node name is ':23' = 'ram16_3'
-- Equation name is 'ram16_3', location is LC5_A16, type is buried.
ram16_3 = DFFE( _EQ028, GLOBAL( clk), VCC, VCC, VCC);
_EQ028 = addr0 & ram16_3
# !_LC4_A14 & ram16_3
# !addr0 & data_i3 & _LC4_A14;
-- Node name is ':22' = 'ram17_0'
-- Equation name is 'ram17_0', location is LC3_A21, type is buried.
ram17_0 = DFFE( _EQ029, GLOBAL( clk), VCC, VCC, VCC);
_EQ029 = !addr0 & ram17_0
# !_LC4_A14 & ram17_0
# addr0 & data_i0 & _LC4_A14;
-- Node name is ':21' = 'ram17_1'
-- Equation name is 'ram17_1', location is LC3_A18, type is buried.
ram17_1 = DFFE( _EQ030, GLOBAL( clk), VCC, VCC, VCC);
_EQ030 = !addr0 & ram17_1
# !_LC4_A14 & ram17_1
# addr0 & data_i1 & _LC4_A14;
-- Node name is ':20' = 'ram17_2'
-- Equation name is 'ram17_2', location is LC3_A19, type is buried.
ram17_2 = DFFE( _EQ031, GLOBAL( clk), VCC, VCC, VCC);
_EQ031 = !addr0 & ram17_2
# !_LC4_A14 & ram17_2
# addr0 & data_i2 & _LC4_A14;
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