ram.vhd

使用VHDL开发的简易数字时钟软件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram is
 generic(width: integer := 4;   -- used to change the memory data's width
    depth: integer := 3);   -- used to change the memery address' width during
             -- instantiation.
 port(
  clk : in std_logic;                           --clock
  addr : in std_logic_vector(depth - 1 downto 0); --address bus
  cs : in std_logic;       --chip select
  wr : in std_logic;       --output enable
             --high for write
             --low for read
  data_i: in std_logic_vector(width - 1 downto 0); --write data bus
  data_o: out std_logic_vector(width - 1 downto 0)  --read data bus
  );
end ram;

architecture Behavioral of ram is

type ram is array(7 downto 0) of std_logic_vector(width - 1 downto 0);
signal ram1  : ram;

begin
 process(clk)
 begin
  if(clk'event and clk = '1') then
    if(cs = '0') then 
      if(wr = '0') then
        data_o <= ram1(conv_integer(addr));
      else
        ram1(conv_integer(addr)) <= data_i;
      end if;
    end if;
  end if;
end process;
end Behavioral;