📄 ring.rpt
字号:
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 3/ 48( 6%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
B: 11/ 96( 11%) 0/ 48( 0%) 9/ 48( 18%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\learning\vhdl\clock\ring.rpt
ring
** EQUATIONS **
freq_h : INPUT;
freq_l : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
RESET : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
secldis0 : INPUT;
secldis1 : INPUT;
secldis2 : INPUT;
secldis3 : INPUT;
-- Node name is 'ALARM'
-- Equation name is 'ALARM', type is output
ALARM = _LC1_B16;
-- Node name is 'light0'
-- Equation name is 'light0', type is output
light0 = _LC2_B16;
-- Node name is 'light1'
-- Equation name is 'light1', type is output
light1 = _LC8_B16;
-- Node name is 'light2'
-- Equation name is 'light2', type is output
light2 = _LC5_B16;
-- Node name is 'light3'
-- Equation name is 'light3', type is output
light3 = _LC1_A13;
-- Node name is 'light4'
-- Equation name is 'light4', type is output
light4 = _LC5_A13;
-- Node name is 'light5'
-- Equation name is 'light5', type is output
light5 = GND;
-- Node name is 'light6'
-- Equation name is 'light6', type is output
light6 = _LC2_A13;
-- Node name is 'light7'
-- Equation name is 'light7', type is output
light7 = GND;
-- Node name is '~590~1'
-- Equation name is '~590~1', location is LC4_B16, type is buried.
-- synthesized logic cell
_LC4_B16 = LCELL( _EQ001);
_EQ001 = freq_h & !sechdis0 & !sechdis2 & !secldis3;
-- Node name is '~590~2'
-- Equation name is '~590~2', location is LC2_B20, type is buried.
-- synthesized logic cell
_LC2_B20 = LCELL( _EQ002);
_EQ002 = _LC4_B20 & !minhdis0 & !secldis1 & !secldis2;
-- Node name is '~661~1'
-- Equation name is '~661~1', location is LC3_B16, type is buried.
-- synthesized logic cell
_LC3_B16 = LCELL( _EQ003);
_EQ003 = !minhdis1 & !minldis2 & !sechdis1 & !secldis0;
-- Node name is '~661~2'
-- Equation name is '~661~2', location is LC6_B16, type is buried.
-- synthesized logic cell
_LC6_B16 = LCELL( _EQ004);
_EQ004 = freq_l & minldis0 & sechdis0 & sechdis2;
-- Node name is '~661~3'
-- Equation name is '~661~3', location is LC5_B20, type is buried.
-- synthesized logic cell
_LC5_B20 = LCELL( _EQ005);
_EQ005 = minhdis0 & !secldis3
# minhdis0 & !secldis1 & !secldis2;
-- Node name is '~661~4'
-- Equation name is '~661~4', location is LC1_B20, type is buried.
-- synthesized logic cell
_LC1_B20 = LCELL( _EQ006);
_EQ006 = _LC5_B20 & _LC6_B16 & minhdis2 & minldis3;
-- Node name is '~661~5'
-- Equation name is '~661~5', location is LC7_B16, type is buried.
-- synthesized logic cell
_LC7_B16 = LCELL( _EQ007);
_EQ007 = _LC2_B20 & _LC4_B16 & !minldis0
# _LC1_B20;
-- Node name is ':661'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ008);
_EQ008 = _LC3_B16 & _LC7_B16 & !minldis1 & !RESET;
-- Node name is '~695~1'
-- Equation name is '~695~1', location is LC3_A13, type is buried.
-- synthesized logic cell
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ009);
_EQ009 = _LC6_A13 & !minldis2;
-- Node name is '~893~1'
-- Equation name is '~893~1', location is LC4_A13, type is buried.
-- synthesized logic cell
_LC4_A13 = LCELL( _EQ010);
_EQ010 = !hourhdis1 & minhdis0 & minhdis1;
-- Node name is '~893~2'
-- Equation name is '~893~2', location is LC4_B20, type is buried.
-- synthesized logic cell
_LC4_B20 = LCELL( _EQ011);
_EQ011 = !minhdis2 & !minldis3;
-- Node name is '~893~3'
-- Equation name is '~893~3', location is LC3_B20, type is buried.
-- synthesized logic cell
_LC3_B20 = LCELL( _EQ012);
_EQ012 = !hourldis0 & !hourldis1 & !hourldis2 & _LC4_B20;
-- Node name is '~893~4'
-- Equation name is '~893~4', location is LC6_A13, type is buried.
-- synthesized logic cell
_LC6_A13 = LCELL( _EQ013);
_EQ013 = !hourhdis0 & hourldis3 & _LC3_B20 & _LC4_A13;
-- Node name is '~893~5'
-- Equation name is '~893~5', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ014);
_EQ014 = _LC6_A13 & minldis2;
-- Node name is '~1176~1'
-- Equation name is '~1176~1', location is LC2_A13, type is buried.
-- synthesized logic cell
_LC2_A13 = LCELL( _EQ015);
_EQ015 = _LC8_A13 & !minldis0 & minldis1 & !RESET;
-- Node name is ':1176'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ016);
_EQ016 = _LC8_A13 & !minldis0 & minldis1 & !RESET;
-- Node name is '~1266~1'
-- Equation name is '~1266~1', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ017);
_EQ017 = _LC3_A13 & !RESET;
-- Node name is ':1266'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ018);
_EQ018 = _LC7_A13 & _LC8_A13 & !minldis1;
-- Node name is ':1296'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ019);
_EQ019 = !_LC3_A13 & minldis0 & minldis1 & !RESET;
-- Node name is ':1326'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ020);
_EQ020 = !_LC3_A13 & minldis0 & !minldis1 & !RESET
# !_LC3_A13 & !minldis0 & minldis1 & !RESET;
-- Node name is ':1356'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ021);
_EQ021 = !_LC3_A13 & !minldis0 & !minldis1 & !RESET;
Project Information e:\learning\vhdl\clock\ring.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,701K
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