📄 alarm4.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** EQUATIONS **
freq_l : INPUT;
hourhdis0 : INPUT;
hourhdis1 : INPUT;
hourldis0 : INPUT;
hourldis1 : INPUT;
hourldis2 : INPUT;
hourldis3 : INPUT;
minhdis0 : INPUT;
minhdis1 : INPUT;
minhdis2 : INPUT;
minldis0 : INPUT;
minldis1 : INPUT;
minldis2 : INPUT;
minldis3 : INPUT;
sechdis0 : INPUT;
sechdis1 : INPUT;
sechdis2 : INPUT;
settime : INPUT;
weekdis0 : INPUT;
weekdis1 : INPUT;
weekdis2 : INPUT;
-- Node name is 'ALARM' = '~512~1'
-- Equation name is 'ALARM', location is LC001, type is output.
ALARM = LCELL( _EQ001 $ GND);
_EQ001 = freq_l & _LC032 & !settime
# ALARM & settime
# ALARM & freq_l & _LC032;
-- Node name is '~498~1'
-- Equation name is '~498~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ002 $ _EQ003);
_EQ002 = !_LC008 & !_LC013 & !_LC031 & sechdis0 & sechdis1 & !sechdis2 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009 & _X010 & _X011 & _X012 & _X013 & _X014
# !_LC008 & !_LC013 & !_LC025 & !_LC031 & minldis0 & !sechdis2 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009 & _X010 & _X011 & _X012 & _X013 & _X014
# !_LC008 & !_LC013 & _LC025 & !_LC031 & !minldis0 & !sechdis2 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009 & _X010 & _X011 & _X012 & _X013 & _X014
# !_LC008 & !_LC013 & !_LC027 & !_LC031 & minldis1 & !sechdis2 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009 & _X010 & _X011 & _X012 & _X013 & _X014;
_X001 = EXP( hourhdis1 & !_LC019);
_X002 = EXP( hourldis2 & !_LC021);
_X003 = EXP( _LC017 & !weekdis2);
_X004 = EXP(!_LC017 & weekdis2);
_X005 = EXP( _LC024 & !weekdis1);
_X006 = EXP(!_LC024 & weekdis1);
_X007 = EXP( _LC020 & !weekdis0);
_X008 = EXP(!_LC020 & weekdis0);
_X009 = EXP(!hourhdis1 & _LC019);
_X010 = EXP(!hourldis2 & _LC021);
_X011 = EXP(!hourhdis0 & _LC018);
_X012 = EXP( hourhdis0 & !_LC018);
_X013 = EXP(!hourldis3 & _LC022);
_X014 = EXP( hourldis3 & !_LC022);
_EQ003 = !_LC008 & !_LC013 & !_LC031 & !sechdis2 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006 & _X007 & _X008 & _X009 & _X010 &
_X011 & _X012 & _X013 & _X014;
_X001 = EXP( hourhdis1 & !_LC019);
_X002 = EXP( hourldis2 & !_LC021);
_X003 = EXP( _LC017 & !weekdis2);
_X004 = EXP(!_LC017 & weekdis2);
_X005 = EXP( _LC024 & !weekdis1);
_X006 = EXP(!_LC024 & weekdis1);
_X007 = EXP( _LC020 & !weekdis0);
_X008 = EXP(!_LC020 & weekdis0);
_X009 = EXP(!hourhdis1 & _LC019);
_X010 = EXP(!hourldis2 & _LC021);
_X011 = EXP(!hourhdis0 & _LC018);
_X012 = EXP( hourhdis0 & !_LC018);
_X013 = EXP(!hourldis3 & _LC022);
_X014 = EXP( hourldis3 & !_LC022);
-- Node name is '~498~2'
-- Equation name is '~498~2', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ004 $ GND);
_EQ004 = _LC027 & !minldis1
# !_LC028 & minldis2
# _LC028 & !minldis2
# !_LC029 & minldis3
# _LC029 & !minldis3;
-- Node name is '~498~3'
-- Equation name is '~498~3', location is LC013, type is buried.
-- synthesized logic cell
_LC013 = LCELL( _EQ005 $ GND);
_EQ005 = !_LC005 & minhdis0
# _LC005 & !minhdis0
# !_LC006 & minhdis1
# _LC006 & !minhdis1
# !_LC007 & minhdis2;
-- Node name is '~498~4'
-- Equation name is '~498~4', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ006 $ GND);
_EQ006 = _LC007 & !minhdis2
# hourldis0 & !_LC002
# !hourldis0 & _LC002
# hourldis1 & !_LC004
# !hourldis1 & _LC004;
-- Node name is '~560~1'
-- Equation name is '~560~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ007 $ GND);
_EQ007 = minldis3 & settime
# _LC029 & !settime
# _LC029 & minldis3;
-- Node name is '~566~1'
-- Equation name is '~566~1', location is LC028, type is buried.
-- synthesized logic cell
_LC028 = LCELL( _EQ008 $ GND);
_EQ008 = minldis2 & settime
# _LC028 & !settime
# _LC028 & minldis2;
-- Node name is '~572~1'
-- Equation name is '~572~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ009 $ GND);
_EQ009 = minldis1 & settime
# _LC027 & !settime
# _LC027 & minldis1;
-- Node name is '~578~1'
-- Equation name is '~578~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ010 $ GND);
_EQ010 = minldis0 & settime
# _LC025 & !settime
# _LC025 & minldis0;
-- Node name is '~584~1'
-- Equation name is '~584~1', location is LC007, type is buried.
-- synthesized logic cell
_LC007 = LCELL( _EQ011 $ GND);
_EQ011 = minhdis2 & settime
# _LC007 & !settime
# _LC007 & minhdis2;
-- Node name is '~590~1'
-- Equation name is '~590~1', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ012 $ GND);
_EQ012 = minhdis1 & settime
# _LC006 & !settime
# _LC006 & minhdis1;
-- Node name is '~596~1'
-- Equation name is '~596~1', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ013 $ GND);
_EQ013 = minhdis0 & settime
# _LC005 & !settime
# _LC005 & minhdis0;
-- Node name is '~602~1'
-- Equation name is '~602~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ014 $ GND);
_EQ014 = hourldis3 & settime
# _LC022 & !settime
# hourldis3 & _LC022;
-- Node name is '~608~1'
-- Equation name is '~608~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ015 $ GND);
_EQ015 = hourldis2 & settime
# _LC021 & !settime
# hourldis2 & _LC021;
-- Node name is '~614~1'
-- Equation name is '~614~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ016 $ GND);
_EQ016 = hourldis1 & settime
# _LC004 & !settime
# hourldis1 & _LC004;
-- Node name is '~620~1'
-- Equation name is '~620~1', location is LC002, type is buried.
-- synthesized logic cell
_LC002 = LCELL( _EQ017 $ GND);
_EQ017 = hourldis0 & settime
# _LC002 & !settime
# hourldis0 & _LC002;
-- Node name is '~626~1'
-- Equation name is '~626~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ018 $ GND);
_EQ018 = hourhdis1 & settime
# _LC019 & !settime
# hourhdis1 & _LC019;
-- Node name is '~632~1'
-- Equation name is '~632~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ019 $ GND);
_EQ019 = hourhdis0 & settime
# _LC018 & !settime
# hourhdis0 & _LC018;
-- Node name is '~638~1'
-- Equation name is '~638~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ020 $ GND);
_EQ020 = settime & weekdis2
# _LC017 & !settime
# _LC017 & weekdis2;
-- Node name is '~644~1'
-- Equation name is '~644~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ021 $ GND);
_EQ021 = settime & weekdis1
# _LC024 & !settime
# _LC024 & weekdis1;
-- Node name is '~650~1'
-- Equation name is '~650~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ022 $ GND);
_EQ022 = settime & weekdis0
# _LC020 & !settime
# _LC020 & weekdis0;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\clock4\clock2\alarm4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,967K
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