📄 alarm4.rpt
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Project Information c:\clock4\clock2\alarm4.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/27/2008 13:18:17
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
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limited to modification, reverse engineering, de-compiling, or use with
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***** Project compilation was successful
ALARM4
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
alarm4 EPM7032LC44-6 21 1 0 21 14 65 %
User Pins: 21 1 0
Project Information c:\clock4\clock2\alarm4.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'secldis3'
Warning: Ignored unnecessary INPUT pin 'secldis2'
Warning: Ignored unnecessary INPUT pin 'secldis1'
Warning: Ignored unnecessary INPUT pin 'secldis0'
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
***** Logic for device 'alarm4' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
h h
s w o o
e e u u
c e r r
h k A h h
d d L d d
i i A V G G G G G i i
s s R C N N N N N s s
2 1 M C D D D D D 1 0
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
sechdis1 | 7 39 | settime
sechdis0 | 8 38 | RESERVED
minldis3 | 9 37 | freq_l
GND | 10 36 | weekdis2
minldis2 | 11 35 | VCC
minldis1 | 12 EPM7032LC44-6 34 | RESERVED
minldis0 | 13 33 | RESERVED
minhdis2 | 14 32 | weekdis0
VCC | 15 31 | RESERVED
minhdis1 | 16 30 | GND
minhdis0 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
h h h h G V R R R R R
o o o o N C E E E E E
u u u u D C S S S S S
r r r r E E E E E
l l l l R R R R R
d d d d V V V V V
i i i i E E E E E
s s s s D D D D D
3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 16/16(100%) 2/16( 12%) 14/36( 38%)
B: LC17 - LC32 13/16( 81%) 6/16( 37%) 16/16(100%) 29/36( 80%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/32 ( 68%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 14/32 ( 43%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 4.47
Total fan-in: 94
Total input pins required: 21
Total output pins required: 1
Total bidirectional pins required: 0
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 85
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 14
Synthesized logic cells: 21/ 32 ( 65%)
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
37 (21) (B) INPUT 0 0 0 0 0 1 0 freq_l
40 (18) (B) INPUT 0 0 0 0 0 0 2 hourhdis0
41 (17) (B) INPUT 0 0 0 0 0 0 2 hourhdis1
21 (16) (A) INPUT 0 0 0 0 0 0 2 hourldis0
20 (15) (A) INPUT 0 0 0 0 0 0 2 hourldis1
19 (14) (A) INPUT 0 0 0 0 0 0 2 hourldis2
18 (13) (A) INPUT 0 0 0 0 0 0 2 hourldis3
17 (12) (A) INPUT 0 0 0 0 0 0 2 minhdis0
16 (11) (A) INPUT 0 0 0 0 0 0 2 minhdis1
14 (10) (A) INPUT 0 0 0 0 0 0 3 minhdis2
13 (9) (A) INPUT 0 0 0 0 0 0 2 minldis0
12 (8) (A) INPUT 0 0 0 0 0 0 3 minldis1
11 (7) (A) INPUT 0 0 0 0 0 0 2 minldis2
9 (6) (A) INPUT 0 0 0 0 0 0 2 minldis3
8 (5) (A) INPUT 0 0 0 0 0 0 1 sechdis0
7 (4) (A) INPUT 0 0 0 0 0 0 1 sechdis1
6 (3) (A) INPUT 0 0 0 0 0 0 1 sechdis2
39 (19) (B) INPUT 0 0 0 0 0 1 16 settime
32 (25) (B) INPUT 0 0 0 0 0 0 2 weekdis0
5 (2) (A) INPUT 0 0 0 0 0 0 2 weekdis1
36 (22) (B) INPUT 0 0 0 0 0 0 2 weekdis2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 1 A OUTPUT s t 0 0 0 2 2 1 0 ALARM
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT s t 15 0 1 12 12 1 0 ~498~1
(25) 31 B SOFT s t 1 0 1 3 3 0 1 ~498~2
(18) 13 A SOFT s t 1 0 1 3 3 0 1 ~498~3
(12) 8 A SOFT s t 1 0 1 3 3 0 1 ~498~4
(27) 29 B LCELL s t 0 0 0 2 1 0 2 ~560~1
(28) 28 B LCELL s t 0 0 0 2 1 0 2 ~566~1
(29) 27 B LCELL s t 0 0 0 2 1 0 3 ~572~1
(32) 25 B LCELL s t 0 0 0 2 1 0 2 ~578~1
(11) 7 A LCELL s t 0 0 0 2 1 0 3 ~584~1
(9) 6 A LCELL s t 0 0 0 2 1 0 2 ~590~1
(8) 5 A LCELL s t 0 0 0 2 1 0 2 ~596~1
(36) 22 B LCELL s t 0 0 0 2 1 0 2 ~602~1
(37) 21 B LCELL s t 0 0 0 2 1 0 2 ~608~1
(7) 4 A LCELL s t 0 0 0 2 1 0 2 ~614~1
(5) 2 A LCELL s t 0 0 0 2 1 0 2 ~620~1
(39) 19 B LCELL s t 0 0 0 2 1 0 2 ~626~1
(40) 18 B LCELL s t 0 0 0 2 1 0 2 ~632~1
(41) 17 B LCELL s t 0 0 0 2 1 0 2 ~638~1
(33) 24 B LCELL s t 0 0 0 2 1 0 2 ~644~1
(38) 20 B LCELL s t 0 0 0 2 1 0 2 ~650~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC1 ALARM
| +------------- LC13 ~498~3
| | +----------- LC8 ~498~4
| | | +--------- LC7 ~584~1
| | | | +------- LC6 ~590~1
| | | | | +----- LC5 ~596~1
| | | | | | +--- LC4 ~614~1
| | | | | | | +- LC2 ~620~1
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> * - - - - - - - | * - | <-- ALARM
LC7 -> - * * * - - - - | * - | <-- ~584~1
LC6 -> - * - - * - - - | * - | <-- ~590~1
LC5 -> - * - - - * - - | * - | <-- ~596~1
LC4 -> - - * - - - * - | * - | <-- ~614~1
LC2 -> - - * - - - - * | * - | <-- ~620~1
Pin
37 -> * - - - - - - - | * - | <-- freq_l
21 -> - - * - - - - * | * - | <-- hourldis0
20 -> - - * - - - * - | * - | <-- hourldis1
17 -> - * - - - * - - | * - | <-- minhdis0
16 -> - * - - * - - - | * - | <-- minhdis1
14 -> - * * * - - - - | * - | <-- minhdis2
39 -> * - - * * * * * | * * | <-- settime
LC32 -> * - - - - - - - | * - | <-- ~498~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\clock4\clock2\alarm4.rpt
alarm4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC32 ~498~1
| +----------------------- LC31 ~498~2
| | +--------------------- LC29 ~560~1
| | | +------------------- LC28 ~566~1
| | | | +----------------- LC27 ~572~1
| | | | | +--------------- LC25 ~578~1
| | | | | | +------------- LC22 ~602~1
| | | | | | | +----------- LC21 ~608~1
| | | | | | | | +--------- LC19 ~626~1
| | | | | | | | | +------- LC18 ~632~1
| | | | | | | | | | +----- LC17 ~638~1
| | | | | | | | | | | +--- LC24 ~644~1
| | | | | | | | | | | | +- LC20 ~650~1
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC31 -> * - - - - - - - - - - - - | - * | <-- ~498~2
LC29 -> - * * - - - - - - - - - - | - * | <-- ~560~1
LC28 -> - * - * - - - - - - - - - | - * | <-- ~566~1
LC27 -> * * - - * - - - - - - - - | - * | <-- ~572~1
LC25 -> * - - - - * - - - - - - - | - * | <-- ~578~1
LC22 -> * - - - - - * - - - - - - | - * | <-- ~602~1
LC21 -> * - - - - - - * - - - - - | - * | <-- ~608~1
LC19 -> * - - - - - - - * - - - - | - * | <-- ~626~1
LC18 -> * - - - - - - - - * - - - | - * | <-- ~632~1
LC17 -> * - - - - - - - - - * - - | - * | <-- ~638~1
LC24 -> * - - - - - - - - - - * - | - * | <-- ~644~1
LC20 -> * - - - - - - - - - - - * | - * | <-- ~650~1
Pin
40 -> * - - - - - - - - * - - - | - * | <-- hourhdis0
41 -> * - - - - - - - * - - - - | - * | <-- hourhdis1
19 -> * - - - - - - * - - - - - | - * | <-- hourldis2
18 -> * - - - - - * - - - - - - | - * | <-- hourldis3
13 -> * - - - - * - - - - - - - | - * | <-- minldis0
12 -> * * - - * - - - - - - - - | - * | <-- minldis1
11 -> - * - * - - - - - - - - - | - * | <-- minldis2
9 -> - * * - - - - - - - - - - | - * | <-- minldis3
8 -> * - - - - - - - - - - - - | - * | <-- sechdis0
7 -> * - - - - - - - - - - - - | - * | <-- sechdis1
6 -> * - - - - - - - - - - - - | - * | <-- sechdis2
39 -> - - * * * * * * * * * * * | * * | <-- settime
32 -> * - - - - - - - - - - - * | - * | <-- weekdis0
5 -> * - - - - - - - - - - * - | - * | <-- weekdis1
36 -> * - - - - - - - - - * - - | - * | <-- weekdis2
LC13 -> * - - - - - - - - - - - - | - * | <-- ~498~3
LC8 -> * - - - - - - - - - - - - | - * | <-- ~498~4
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