📄 picoblazeinput.vhd
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-- Company: Steepest Ascent
-- Engineer: James A Bowman
--
-- Create Date:
-- Design Name: picoblaze_traffic_light
-- Module Name: picoblazeinput - Behavioral
-- Project Name: XUP- PicoBlaze Traffic Light Example
-- Target Device: XILINX Virtex II Pro XC2VP30
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: Version 1.1
-- Additional
-- Comments: Version 1.1 Input bus width increased to 8 Bits
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PicoBlazeInput is
Port ( input_0 : in std_logic_vector(7 downto 0);
input_1 : in std_logic_vector(7 downto 0);
input_2 : in std_logic_vector(7 downto 0);
input_3 : in std_logic_vector(7 downto 0);
clk : in std_logic;
input_id : in std_logic_vector(7 downto 0);
input_data : out std_logic_vector(7 downto 0));
end PicoBlazeInput;
architecture Behavioral of PicoBlazeInput is
signal input_intermediate : std_logic_vector(7 downto 0):= "00000000";
signal mux_input : std_logic_vector(1 downto 0):= "00";
begin
-- Setup for Maximum of 4 Inputs (2 Bit Address)
mux_input <= input_id(1 downto 0);
process(clk)
begin
if rising_edge(clk) then
-- Each Output is Full Data Width Wide (8 Bits)
MUX: case mux_input is
when "00" =>
input_intermediate <= input_0;
when "01" =>
input_intermediate <= input_1;
when "10" =>
input_intermediate <= input_2;
when "11" =>
input_intermediate <= input_3;
when others =>
input_intermediate <= "00000000";
end case;
end if;
input_data <= input_intermediate;
end process;
end Behavioral;
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