clockdivider.vhd

此为VHDL实现的路口红绿灯控制例子

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-- Company:			Steepest Ascent
-- Engineer:		James A Bowman
--
-- Create Date:   
-- Design Name:   picoblaze_traffic_light 
-- Module Name:   clockdivider - Behavioral
-- Project Name:  XUP- PicoBlaze Traffic Light Example 
-- Target Device: XILINX Virtex II Pro XC2VP30
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:		Version 1.0
-- Additional 
-- Comments:		None
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity clockdivider is
    Port ( clk        : in std_logic;
	 		  reset		 : in std_logic;
           clk_divide : out std_logic);
end clockdivider;


architecture Behavioral of clockdivider is

signal count_val  : std_logic_vector(26 downto 0):= (others => '0');
signal temp_output: std_logic:= '0';

begin

	process(clk, reset)
		begin
			if (reset = '0') then		-- If Reset
				temp_output <= '0';
			elsif rising_edge(clk) then
				
				-- Value set to 49999999 (1/2 of 100 MHz minus 1)
				if (count_val = "10111110101111000001111111") then 	-- Implementation			  
				
				-- Value set to 7 (8 Clock Cycles minus 1)
				--if (count_val = "0000000000000000000000111") then	-- Simulation
				
					count_val <= (others => '0');
					temp_output <= not(temp_output);
				else
					count_val <= count_val + 1;
				end if;
			end if;

			-- Update Output Value
			clk_divide <= temp_output;

	end process;

end Behavioral;