📄 picoblazeoutput.vhd
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-- Company: Steepest Ascent
-- Engineer: James A Bowman
--
-- Create Date:
-- Design Name: picoblaze_traffic_light
-- Module Name: picoblazeoutput - Behavioral
-- Project Name: XUP- PicoBlaze Traffic Light Example
-- Target Device: XILINX Virtex II Pro XC2VP30
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision: Version 1.0
-- Additional
-- Comments: None
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PicoBlazeOutput is
Port ( output_data : in std_logic_vector(7 downto 0);
clk : in std_logic;
output_0 : out std_logic_vector(7 downto 0);
output_1 : out std_logic_vector(7 downto 0);
output_2 : out std_logic_vector(7 downto 0);
output_3 : out std_logic_vector(7 downto 0);
output_id : in std_logic_vector(7 downto 0);
output_we : in std_logic);
end PicoBlazeOutput;
architecture Behavioral of PicoBlazeOutput is
signal data_intermediate : std_logic_vector(7 downto 0):= "00000000";
signal mux_input : std_logic_vector(1 downto 0):= "00";
begin
-- Setup for Maximum of 4 Ouputs (2 Bit Address)
mux_input <= output_id(1 downto 0);
process(clk)
begin
if rising_edge(clk) then
-- Each Output is Full Data Width Wide (8 Bits)
if (output_we = '1') then
if mux_input ="00" then
output_0 <= output_data;
end if;
if mux_input ="01" then
output_1 <= output_data;
end if;
if mux_input ="10" then
output_2 <= output_data;
end if;
if mux_input ="11" then
output_3 <= output_data;
end if;
end if;
end if;
end process;
end Behavioral;
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