picoblaze_trafficlight_tb.vhd

此为VHDL实现的路口红绿灯控制例子

--------------------------------------------------------------------------------
-- Company:			Steepest Ascent
-- Engineer:		James A Bowman
--
-- Create Date:   
-- Design Name:   picoblaze_traffic_light 
-- Module Name:   picoblaze_trafficlight_TB.vhd
-- Project Name:  TrafficLightFSM
-- Target Device: XILINX Virtex II Pro XC2VP30
-- Tool versions:  
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trafficlightfsm
--
-- Dependencies:
-- 
-- Revision:		Version 1.0
-- Additional 
-- Comments:		None
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY picoblaze_trafficlight_TB_vhd IS
END picoblaze_trafficlight_TB_vhd;

ARCHITECTURE behavior OF picoblaze_trafficlight_TB_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT picoblaze_trafficlight
	PORT(
		btn1_in 	: IN std_logic;
		btn2_in 	: IN std_logic;
		clk 		: IN std_logic;
		reset 	: IN std_logic;          
		led_out 	: OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL btn1_in :  std_logic := '0';
	SIGNAL btn2_in :  std_logic := '0';
	SIGNAL clk 		:  std_logic := '0';
	SIGNAL reset 	:  std_logic := '0';

	--Outputs
	SIGNAL led_out :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: picoblaze_trafficlight PORT MAP(
		btn1_in => btn1_in,
		btn2_in => btn2_in,
			 clk => clk,
		  reset => reset,
		  led_out => led_out
	);

  	-- Set-up Clock
	clk <= not clk after 1 ns; 

	tb : PROCESS
	BEGIN
		btn1_in <= '1';
		btn2_in <= '1';
		reset   <= '1';
		
		-- Wait 10 ns for global reset to finish
		wait for 10 ns;

		-- Place stimulus here
		wait for 100 ns;
		btn1_in <= '0';		-- System Reset State 1
		wait for 100 ns;
		btn1_in <= '1';		
		btn2_in <= '0';		-- Pedestian Button (Activates FSM)
		wait for 50 ns;
		btn2_in <= '1';
		wait; 					-- will wait forever
	END PROCESS;

END;