📄 traffic.rpt
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Total fast input logic cells required: 0
Total output pins required: 20
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 95
Total flipflops required: 39
Total product terms required: 336
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 50
Synthesized logic cells: 15/ 128 ( 11%)
Device-Specific Information: c:\maxplus2\files\max\traffic\traffic.rpt
traffic
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clock
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\files\max\traffic\traffic.rpt
traffic
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
30 37 C FF t 0 0 0 0 12 1 0 led0 (:748)
31 35 C FF t 0 0 0 0 12 1 0 led1 (:747)
33 64 D FF t 0 0 0 0 12 1 0 led2 (:746)
34 61 D FF t 0 0 0 0 12 1 0 led3 (:745)
35 59 D FF t 0 0 0 0 12 1 0 led4 (:744)
36 57 D FF t 0 0 0 0 12 1 0 led5 (:743)
37 56 D FF t 0 0 0 0 12 1 0 led6 (:742)
39 53 D FF t 0 0 0 0 12 1 0 led7 (:741)
51 77 E OUTPUT s t 0 0 0 0 2 0 0 slcs0
52 80 E OUTPUT s t 0 0 0 0 2 0 0 slcs1
54 83 F OUTPUT s t 0 0 0 0 2 0 0 slcs2
55 85 F OUTPUT s t 0 0 0 0 2 0 0 slcs3
40 51 D OUTPUT s t 0 0 0 0 4 0 0 sled0
41 49 D OUTPUT s t 0 0 0 0 4 0 0 sled1
44 65 E OUTPUT s t 0 0 0 0 4 0 0 sled2
45 67 E OUTPUT s t 0 0 0 0 4 0 0 sled3
46 69 E OUTPUT s t 0 0 0 0 4 0 0 sled4
48 72 E OUTPUT s t 0 0 0 0 4 0 0 sled5
49 73 E OUTPUT s t 0 0 0 0 4 0 0 sled6
50 75 E OUTPUT t 0 0 0 0 0 0 0 sled7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\max\traffic\traffic.rpt
traffic
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 18 B SOFT t 0 0 0 0 8 0 3 |lpm_add_sub:1105|addcore:adder|addcore:adder0|cout_node
(75) 118 H SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node1
- 119 H SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node2
- 22 B SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node3
(18) 24 B SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node4
(17) 25 B SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node5
- 26 B SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node6
(20) 21 B SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node7
(21) 19 B SOFT t 0 0 0 0 9 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node0
- 28 B SOFT t 0 0 0 0 10 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node1
- 30 B SOFT t 0 0 0 0 12 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node3
(60) 93 F SOFT t 0 0 0 0 13 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node4
(57) 88 F SOFT t 0 0 0 0 14 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node5
(62) 96 F SOFT t 0 0 0 0 15 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node6
- 95 F SOFT t 0 0 0 0 16 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node7
(61) 94 F SOFT t 0 0 0 0 17 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder2|result_node0
- 84 F SOFT t 0 0 0 0 18 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder2|result_node1
(56) 86 F SOFT t 0 0 0 0 12 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder2|result_node2
(58) 91 F SOFT t 0 0 0 0 13 0 1 |lpm_add_sub:1105|addcore:adder|addcore:adder2|result_node3
- 122 H SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1106|addcore:adder|g4
- 127 H SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:1106|addcore:adder|result_node1
- 54 D SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1106|addcore:adder|result_node2
- 63 D SOFT t 0 0 0 0 4 0 3 |lpm_add_sub:1106|addcore:adder|result_node3
- 42 C SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1106|addcore:adder|result_node5
(25) 45 C SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1106|addcore:adder|result_node6
(23) 48 C SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1106|addcore:adder|result_node7
- 62 D SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1107|addcore:adder|g4
- 116 H SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:1107|addcore:adder|result_node1
(73) 115 H SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1107|addcore:adder|result_node2
- 60 D SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:1107|addcore:adder|result_node3
- 44 C SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1107|addcore:adder|result_node5
(24) 46 C SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1107|addcore:adder|result_node6
- 47 C SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1107|addcore:adder|result_node7
- 124 H SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1108|addcore:adder|g4
(79) 125 H SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:1108|addcore:adder|result_node1
- 114 H SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:1108|addcore:adder|result_node2
- 50 D SOFT t 0 0 0 0 4 0 3 |lpm_add_sub:1108|addcore:adder|result_node3
- 52 D SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:1108|addcore:adder|result_node5
- 39 C SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:1108|addcore:adder|result_node6
- 34 C SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:1108|addcore:adder|result_node7
- 102 G DFFE + t 4 3 1 0 17 0 22 count19 (:178)
- 100 G DFFE + t 4 3 1 0 17 0 23 count18 (:179)
(65) 101 G DFFE + t 4 3 1 0 17 0 24 count17 (:180)
- 98 G DFFE + t 4 3 1 0 17 0 25 count16 (:181)
(63) 97 G DFFE + t 4 3 1 0 17 0 26 count15 (:182)
- 66 E DFFE + t 4 3 1 0 17 0 27 count14 (:183)
(69) 107 G DFFE + t 4 3 1 0 17 0 28 count13 (:184)
- 92 F DFFE + t 4 3 1 0 17 4 33 count12 (:185)
- 81 F DFFE + t 4 3 1 0 17 4 33 count11 (:186)
- 82 F DFFE + t 4 0 1 0 20 0 30 count10 (:187)
- 87 F DFFE + t 4 3 1 0 17 0 31 count9 (:188)
- 90 F DFFE + t 4 3 1 0 17 0 32 count8 (:189)
- 68 E DFFE + t 4 3 1 0 17 0 32 count7 (:190)
- 74 E DFFE + t 4 3 1 0 17 0 33 count6 (:191)
- 76 E DFFE + t 4 3 1 0 17 0 34 count5 (:192)
- 79 E DFFE + t 4 3 1 0 17 0 35 count4 (:193)
- 78 E DFFE + t 4 3 1 0 17 0 16 count3 (:194)
- 71 E DFFE + t 4 3 1 0 17 0 17 count2 (:195)
- 70 E DFFE + t 4 3 1 0 17 0 18 count1 (:196)
- 89 F DFFE + t 4 3 1 0 17 0 19 count0 (:197)
- 106 G TFFE + t 7 3 0 0 16 8 10 sec_tick (:203)
- 58 D DFFE t 3 0 1 0 14 8 14 lamp_time7 (:543)
- 121 H DFFE t 3 0 1 0 14 8 17 lamp_time6 (:544)
- 55 D DFFE t 13 1 0 0 14 8 20 lamp_time5 (:545)
- 113 H DFFE t 12 1 0 0 14 8 20 lamp_time4 (:546)
(27) 43 C DFFE t 3 0 1 0 14 8 26 lamp_time3 (:547)
- 41 C DFFE t 7 4 0 0 16 8 29 lamp_time2 (:548)
(28) 40 C DFFE t 7 4 0 0 16 8 32 lamp_time1 (:549)
(29) 38 C TFFE t 1 0 1 0 11 8 29 lamp_time0 (:550)
- 36 C TFFE t 0 0 0 0 11 8 10 lamp_status1 (:591)
- 33 C TFFE t 0 0 0 0 10 8 9 lamp_status0 (:592)
(80) 126 H LCELL s t 0 0 0 0 4 7 0 ~793~1
(81) 128 H LCELL s t 0 0 0 0 4 7 0 ~794~1
(77) 123 H LCELL s t 0 0 0 0 4 7 0 ~795~1
(74) 117 H LCELL s t 0 0 0 0 4 7 0 ~796~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\max\traffic\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC18 |lpm_add_sub:1105|addcore:adder|addcore:adder0|cout_node
| +--------------- LC22 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node3
| | +------------- LC24 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node4
| | | +----------- LC25 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node5
| | | | +--------- LC26 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node6
| | | | | +------- LC21 |lpm_add_sub:1105|addcore:adder|addcore:adder0|result_node7
| | | | | | +----- LC19 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node0
| | | | | | | +--- LC28 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node1
| | | | | | | | +- LC30 |lpm_add_sub:1105|addcore:adder|addcore:adder1|result_node3
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
83 -> - - - - - - - - - | - - - - - - - - | <-- clock
LC81 -> - - - - - - - - * | - * - - * * * * | <-- count11
LC82 -> - - - - - - - - * | - * - - * * * - | <-- count10
LC87 -> - - - - - - - * * | - * - - * * * - | <-- count9
LC90 -> - - - - - - * * * | - * - - * * * - | <-- count8
LC68 -> * - - - - * * * * | - * - - * * * - | <-- count7
LC74 -> * - - - * * * * * | - * - - * * * - | <-- count6
LC76 -> * - - * * * * * * | - * - - * * * - | <-- count5
LC79 -> * - * * * * * * * | - * - - * * * - | <-- count4
LC78 -> * * * * * * * * * | - * - - - * - - | <-- count3
LC71 -> * * * * * * * * * | - * - - - * - * | <-- count2
LC70 -> * * * * * * * * * | - * - - - * - * | <-- count1
LC89 -> * * * * * * * * * | - * - - - * - * | <-- count0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\max\traffic\traffic.rpt
traffic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC37 led0
| +----------------------------- LC35 led1
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