📄 transform.vhd
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--Declaration of using IEEE Library
Library IEEE;
--Declaration of using STD_LOGIC_1164 package
Use IEEE.std_logic_1164.all;
--Declaration of using STD_LOGIC_UNSIGNED package
Use IEEE.std_logic_unsigned.all;
--Declaration of Entity transform
Entity transform is
Port( ai:in std_logic_vector(3 downto 0); --Declaration of in port
b:out std_logic_vector(6 downto 0)); --Declaration of out ports
End transform;
--Declaration of Architecture bav
Architecture bav of transform is
Begin
process(ai)
begin
case ai is
when "0000"=>b<="1111110";
when "0001"=>b<="0110000";
when "0010"=>b<="1101101";
when "0011"=>b<="1111001";
when "0100"=>b<="0110011";
when "0101"=>b<="1011011";
when "0110"=>b<="1011111";
when "0111"=>b<="1110000";
when "1000"=>b<="1111111";
when "1001"=>b<="1111011";
when others=>b<="0000000";
end case;
end process;
End bav;
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