asm_led.tan.rpt

本程序是一个用VHDL编写的数码管扫描显示控制器的设计与实现的程序

; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; x[4]      ; x[3]      ; clk        ; clk      ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tsu                                                              ;
+-------+--------------+------------+-------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To        ; To Clock ;
+-------+--------------+------------+-------+-----------+----------+
; N/A   ; None         ; 11.000 ns  ; reset ; x[3]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; x[1]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; x[2]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; x[5]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; x[0]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; x[4]      ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; c[1]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; c[2]~reg0 ; clk      ;
; N/A   ; None         ; 11.000 ns  ; reset ; c[0]~reg0 ; clk      ;
+-------+--------------+------------+-------+-----------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[5]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[5]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[5]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[3]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[3]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[3]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[1]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[1]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[1]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[0]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[0]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[0]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[6]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[6]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[6]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[4]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[4]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[4]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[1]~reg0 ; d[2]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[2]~reg0 ; d[2]    ; clk        ;
; N/A   ; None         ; 17.000 ns  ; c[0]~reg0 ; d[2]    ; clk        ;
; N/A   ; None         ; 8.000 ns   ; c[0]~reg0 ; c[0]    ; clk        ;
; N/A   ; None         ; 8.000 ns   ; c[2]~reg0 ; c[2]    ; clk        ;
; N/A   ; None         ; 8.000 ns   ; c[1]~reg0 ; c[1]    ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[0]      ; catn[0] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[5]      ; catn[5] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[2]      ; catn[2] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[1]      ; catn[1] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[4]      ; catn[4] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; x[3]      ; catn[3] ; clk        ;
+-------+--------------+------------+-----------+---------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; -3.000 ns ; reset ; x[3]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; x[1]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; x[2]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; x[5]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; x[0]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; x[4]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; c[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; c[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; reset ; c[0]~reg0 ; clk      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 27 16:14:11 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off asm_led -c asm_led
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 47.62 MHz between source register "x[3]" and destination register "x[0]" (period= 21.0 ns)
    Info: + Longest register to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP57; Fanout = 1; COMB Node = 'Mux~546'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC49; Fanout = 18; REG Node = 'x[0]'
        Info: Total cell delay = 14.000 ns ( 87.50 % )
        Info: Total interconnect delay = 2.000 ns ( 12.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC49; Fanout = 18; REG Node = 'x[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "x[3]" (data pin = "reset", clock pin = "clk") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 16; PIN Node = 'reset'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "d[5]" through register "c[1]~reg0" is 17.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC11; Fanout = 16; REG Node = 'c[1]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC11; Fanout = 16; REG Node = 'c[1]~reg0'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'transform:u1|b[5]~495'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'd[5]'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: th for register "x[3]" (data pin = "reset", clock pin = "clk") is -3.000 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 16; PIN Node = 'reset'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC56; Fanout = 18; REG Node = 'x[3]'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Apr 27 16:14:11 2006
    Info: Elapsed time: 00:00:01