light.map.qmsg

这是一个用VHDL编写的发光二极管走马灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 19 10:56:06 2006 " "Info: Processing started: Fri May 19 10:56:06 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off light -c light " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off light -c light" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "light.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file light.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 light-light_arch " "Info: Found design unit 1: light-light_arch" {  } { { "D:/YES OR NO/light/light.vhd" "light-light_arch" "" { Text "D:/YES OR NO/light/light.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 light " "Info: Found entity 1: light" {  } { { "D:/YES OR NO/light/light.vhd" "light" "" { Text "D:/YES OR NO/light/light.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adad.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file ../adad.vhd" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a light.vhd(18) " "Warning: VHDL Process Statement warning at light.vhd(18): signal a is in statement, but is not in sensitivity list" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a light.vhd(23) " "Warning: VHDL Process Statement warning at light.vhd(23): signal a is in statement, but is not in sensitivity list" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a light.vhd(42) " "Warning: VHDL Process Statement warning at light.vhd(42): signal a is in statement, but is not in sensitivity list" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a light.vhd(47) " "Warning: VHDL Process Statement warning at light.vhd(47): signal a is in statement, but is not in sensitivity list" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ld light.vhd(11) " "Warning: VHDL Process Statement warning at light.vhd(11): signal or variable ld may not be assigned a new value in every possible path through the Process Statement. Signal or variable ld holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[7\]\$latch " "Warning: LATCH primitive ld\[7\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[6\]\$latch " "Warning: LATCH primitive ld\[6\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[5\]\$latch " "Warning: LATCH primitive ld\[5\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[4\]\$latch " "Warning: LATCH primitive ld\[4\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[3\]\$latch " "Warning: LATCH primitive ld\[3\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[2\]\$latch " "Warning: LATCH primitive ld\[2\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[1\]\$latch " "Warning: LATCH primitive ld\[1\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "ld\[8\]\$latch " "Warning: LATCH primitive ld\[8\]\$latch is permanently enabled" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 11 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clo " "Info: Promoted clock signal driven by pin clo to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "35 " "Info: Implemented 35 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "16 " "Info: Implemented 16 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "8 " "Info: Implemented 8 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 19 10:56:11 2006 " "Info: Processing ended: Fri May 19 10:56:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}