📄 light.tan.qmsg
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{ "Info" "ITDB_FULL_TCO_RESULT" "clo ld\[3\] a\[2\] 17.000 ns register " "Info: tco from clock clo to destination pin ld\[3\] through register a\[2\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo source 3.000 ns + Longest register " "Info: + Longest clock path from clock clo to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[2\] 1 REG LC36 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns ld\[3\]\$latch\$d_and~12 2 COMB LC40 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'ld\[3\]\$latch\$d_and~12'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "9.000 ns" { a[2] ld[3]$latch$d_and~12 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns ld\[3\] 3 PIN PIN_28 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'ld\[3\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "4.000 ns" { ld[3]$latch$d_and~12 ld[3] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "13.000 ns" { a[2] ld[3]$latch$d_and~12 ld[3] } "NODE_NAME" } } } } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "13.000 ns" { a[2] ld[3]$latch$d_and~12 ld[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sw1 ld\[3\] 15.000 ns Longest " "Info: Longest tpd from source pin sw1 to destination pin ld\[3\] is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns sw1 1 PIN PIN_54 45 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 45; PIN Node = 'sw1'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { sw1 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns ld\[3\]\$latch\$d_and~12 2 COMB LC40 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'ld\[3\]\$latch\$d_and~12'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "9.000 ns" { sw1 ld[3]$latch$d_and~12 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld\[3\] 3 PIN PIN_28 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'ld\[3\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "4.000 ns" { ld[3]$latch$d_and~12 ld[3] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "15.000 ns" { sw1 ld[3]$latch$d_and~12 ld[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "a\[2\] btn2 clo -3.000 ns register " "Info: th for register a\[2\] (data pin = btn2, clock pin = clo) is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo destination 3.000 ns + Longest register " "Info: + Longest clock path from clock clo to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 36 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "7.000 ns" { btn2 a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 a[2] } "NODE_NAME" } } } } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 a[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clo ld\[5\] a\[3\] 17.000 ns register " "Info: Minimum tco from clock clo to destination pin ld\[5\] through register a\[3\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clo to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a\[3\] 2 REG LC39 38 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 38; REG Node = 'a\[3\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a[3] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[3\] 1 REG LC39 38 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 38; REG Node = 'a\[3\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { a[3] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns ld\[5\]\$latch\$d_and~11 2 COMB LC37 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'ld\[5\]\$latch\$d_and~11'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "9.000 ns" { a[3] ld[5]$latch$d_and~11 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns ld\[5\] 3 PIN PIN_30 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ld\[5\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "4.000 ns" { ld[5]$latch$d_and~11 ld[5] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "13.000 ns" { a[3] ld[5]$latch$d_and~11 ld[5] } "NODE_NAME" } } } } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[3] } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "13.000 ns" { a[3] ld[5]$latch$d_and~11 ld[5] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "btn2 ld\[5\] 15.000 ns Shortest " "Info: Shortest tpd from source pin btn2 to destination pin ld\[5\] is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 36 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns ld\[5\]\$latch\$d_and~11 2 COMB LC37 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'ld\[5\]\$latch\$d_and~11'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "8.000 ns" { btn2 ld[5]$latch$d_and~11 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld\[5\] 3 PIN PIN_30 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ld\[5\]'" { } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "4.000 ns" { ld[5]$latch$d_and~11 ld[5] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" { } { } 0} } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "15.000 ns" { btn2 ld[5]$latch$d_and~11 ld[5] } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 19 10:56:22 2006 " "Info: Processing ended: Fri May 19 10:56:22 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
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