📄 light.tan.rpt
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; N/A ; None ; 15.000 ns ; btn2 ; ld[6] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[2] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[2] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[4] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[4] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[7] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[7] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[8] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[8] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[1] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[1] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[5] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[5] ;
+-------+-------------------+-----------------+------+-------+
+------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A ; None ; -3.000 ns ; btn2 ; a[2] ; clo ;
; N/A ; None ; -3.000 ns ; btn2 ; a[1] ; clo ;
; N/A ; None ; -3.000 ns ; btn2 ; a[0] ; clo ;
; N/A ; None ; -3.000 ns ; btn2 ; a[3] ; clo ;
; N/A ; None ; -3.000 ns ; sw1 ; a[2] ; clo ;
; N/A ; None ; -3.000 ns ; sw1 ; a[1] ; clo ;
; N/A ; None ; -3.000 ns ; sw1 ; a[0] ; clo ;
; N/A ; None ; -3.000 ns ; sw1 ; a[3] ; clo ;
+---------------+-------------+-----------+------+------+----------+
+-------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+------+-------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+------+-------+------------+
; N/A ; None ; 17.000 ns ; a[3] ; ld[5] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[5] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[5] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[5] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[1] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[1] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[1] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[1] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[8] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[8] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[8] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[8] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[7] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[7] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[7] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[7] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[4] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[4] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[4] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[4] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[2] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[2] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[2] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[2] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[6] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[6] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[6] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[6] ; clo ;
; N/A ; None ; 17.000 ns ; a[3] ; ld[3] ; clo ;
; N/A ; None ; 17.000 ns ; a[0] ; ld[3] ; clo ;
; N/A ; None ; 17.000 ns ; a[1] ; ld[3] ; clo ;
; N/A ; None ; 17.000 ns ; a[2] ; ld[3] ; clo ;
+---------------+------------------+----------------+------+-------+------------+
+--------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+------+-------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+-------+
; N/A ; None ; 15.000 ns ; btn2 ; ld[5] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[5] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[1] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[1] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[8] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[8] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[7] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[7] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[4] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[4] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[2] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[2] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[6] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[6] ;
; N/A ; None ; 15.000 ns ; btn2 ; ld[3] ;
; N/A ; None ; 15.000 ns ; sw1 ; ld[3] ;
+---------------+-------------------+-----------------+------+-------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Fri May 19 10:56:21 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off light -c light
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clo is an undefined clock
Info: Clock clo has Internal fmax of 76.92 MHz between source register a[2] and destination register a~0 (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC46; Fanout = 2; REG Node = 'a~0'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock clo to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC46; Fanout = 2; REG Node = 'a~0'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock clo to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register a[2] (data pin = btn2, clock pin = clo) is 11.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'
Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 9.000 ns ( 90.00 % )
Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock clo to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock clo to destination pin ld[3] through register a[2] is 17.000 ns
Info: + Longest clock path from clock clo to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 13.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'ld[3]$latch$d_and~12'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'ld[3]'
Info: Total cell delay = 11.000 ns ( 84.62 % )
Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Longest tpd from source pin sw1 to destination pin ld[3] is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 45; PIN Node = 'sw1'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC40; Fanout = 1; COMB Node = 'ld[3]$latch$d_and~12'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'ld[3]'
Info: Total cell delay = 13.000 ns ( 86.67 % )
Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: th for register a[2] (data pin = btn2, clock pin = clo) is -3.000 ns
Info: + Longest clock path from clock clo to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'
Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a[2]'
Info: Total cell delay = 9.000 ns ( 90.00 % )
Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Minimum tco from clock clo to destination pin ld[5] through register a[3] is 17.000 ns
Info: + Shortest clock path from clock clo to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 38; REG Node = 'a[3]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Shortest register to pin delay is 13.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 38; REG Node = 'a[3]'
Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'ld[5]$latch$d_and~11'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ld[5]'
Info: Total cell delay = 11.000 ns ( 84.62 % )
Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Shortest tpd from source pin btn2 to destination pin ld[5] is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'
Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'ld[5]$latch$d_and~11'
Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'ld[5]'
Info: Total cell delay = 14.000 ns ( 93.33 % )
Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri May 19 10:56:22 2006
Info: Elapsed time: 00:00:00
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