seg7_b.tan.rpt

这是一个用VHDL语言编写的数字电路程序

Timing Analyzer report for seg7_b
Thu Apr 06 17:18:29 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                   ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From  ; To    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 15.000 ns   ; a2[0] ; c2[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;       ;       ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------+-------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+-------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To    ;
+-------+-------------------+-----------------+-------+-------+
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[3] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[3] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[3] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[3] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[6] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[6] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[6] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[6] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[5] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[5] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[5] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[5] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[4] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[4] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[4] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[4] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[1] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[1] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[1] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[1] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[0] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[0] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[0] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[0] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; b2[2] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; b2[2] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; b2[2] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; b2[2] ;
; N/A   ; None              ; 15.000 ns       ; a2[3] ; c2[3] ;
; N/A   ; None              ; 15.000 ns       ; a2[2] ; c2[2] ;
; N/A   ; None              ; 15.000 ns       ; a2[1] ; c2[1] ;
; N/A   ; None              ; 15.000 ns       ; a2[0] ; c2[0] ;
+-------+-------------------+-----------------+-------+-------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 06 17:18:29 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg7_b -c seg7_b
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Longest tpd from source pin "a2[0]" to destination pin "b2[3]" is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 13; PIN Node = 'a2[0]'
    Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'seg7:comp1|b1_out[3]~1007'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'b2[3]'
    Info: Total cell delay = 13.000 ns ( 86.67 % )
    Info: Total interconnect delay = 2.000 ns ( 13.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Apr 06 17:18:29 2006
    Info: Elapsed time: 00:00:01