seg7_b.map.qmsg

这是一个用VHDL语言编写的数字电路程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 06 17:18:20 2006 " "Info: Processing started: Thu Apr 06 17:18:20 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg7_b -c seg7_b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg7_b -c seg7_b" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vhdl1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7-seg7_arch " "Info: Found design unit 1: seg7-seg7_arch" {  } { { "Vhdl1.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/Vhdl1.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7 " "Info: Found entity 1: seg7" {  } { { "Vhdl1.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/Vhdl1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_b-seg7_arch " "Info: Found design unit 1: seg7_b-seg7_arch" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_b " "Info: Found entity 1: seg7_b" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg7_b " "Info: Elaborating entity \"seg7_b\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7 seg7:comp1 " "Info: Elaborating entity \"seg7\" for hierarchy \"seg7:comp1\"" {  } { { "seg7_b.vhd" "comp1" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 19 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[0\] GND " "Warning: Pin \"catn\[0\]\" stuck at GND" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[1\] VCC " "Warning: Pin \"catn\[1\]\" stuck at VCC" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[2\] VCC " "Warning: Pin \"catn\[2\]\" stuck at VCC" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[3\] VCC " "Warning: Pin \"catn\[3\]\" stuck at VCC" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[4\] VCC " "Warning: Pin \"catn\[4\]\" stuck at VCC" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "catn\[5\] VCC " "Warning: Pin \"catn\[5\]\" stuck at VCC" {  } { { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "17 " "Info: Implemented 17 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 06 17:18:22 2006 " "Info: Processing ended: Thu Apr 06 17:18:22 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}