seg7_b.hier_info

这是一个用VHDL语言编写的数字电路程序

|seg7_b
a2[0] => seg7:comp1.a1_in[0]
a2[0] => c2[0].DATAIN
a2[1] => seg7:comp1.a1_in[1]
a2[1] => c2[1].DATAIN
a2[2] => seg7:comp1.a1_in[2]
a2[2] => c2[2].DATAIN
a2[3] => seg7:comp1.a1_in[3]
a2[3] => c2[3].DATAIN
c2[0] <= a2[0].DB_MAX_OUTPUT_PORT_TYPE
c2[1] <= a2[1].DB_MAX_OUTPUT_PORT_TYPE
c2[2] <= a2[2].DB_MAX_OUTPUT_PORT_TYPE
c2[3] <= a2[3].DB_MAX_OUTPUT_PORT_TYPE
b2[0] <= seg7:comp1.b1_out[0]
b2[1] <= seg7:comp1.b1_out[1]
b2[2] <= seg7:comp1.b1_out[2]
b2[3] <= seg7:comp1.b1_out[3]
b2[4] <= seg7:comp1.b1_out[4]
b2[5] <= seg7:comp1.b1_out[5]
b2[6] <= seg7:comp1.b1_out[6]
catn[0] <= <GND>
catn[1] <= <VCC>
catn[2] <= <VCC>
catn[3] <= <VCC>
catn[4] <= <VCC>
catn[5] <= <VCC>


|seg7_b|seg7:comp1
a1_in[0] => Mux~0.IN19
a1_in[0] => Mux~1.IN19
a1_in[0] => Mux~2.IN19
a1_in[0] => Mux~3.IN19
a1_in[0] => Mux~4.IN19
a1_in[0] => Mux~5.IN19
a1_in[0] => Mux~6.IN19
a1_in[1] => Mux~0.IN18
a1_in[1] => Mux~1.IN18
a1_in[1] => Mux~2.IN18
a1_in[1] => Mux~3.IN18
a1_in[1] => Mux~4.IN18
a1_in[1] => Mux~5.IN18
a1_in[1] => Mux~6.IN18
a1_in[2] => Mux~0.IN17
a1_in[2] => Mux~1.IN17
a1_in[2] => Mux~2.IN17
a1_in[2] => Mux~3.IN17
a1_in[2] => Mux~4.IN17
a1_in[2] => Mux~5.IN17
a1_in[2] => Mux~6.IN17
a1_in[3] => Mux~0.IN16
a1_in[3] => Mux~1.IN16
a1_in[3] => Mux~2.IN16
a1_in[3] => Mux~3.IN16
a1_in[3] => Mux~4.IN16
a1_in[3] => Mux~5.IN16
a1_in[3] => Mux~6.IN16
b1_out[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
b1_out[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
b1_out[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
b1_out[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
b1_out[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
b1_out[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
b1_out[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE