seg7_b.tan.qmsg

这是一个用VHDL语言编写的数字电路程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 06 17:18:29 2006 " "Info: Processing started: Thu Apr 06 17:18:29 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off seg7_b -c seg7_b " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg7_b -c seg7_b" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a2\[0\] b2\[3\] 15.000 ns Longest " "Info: Longest tpd from source pin \"a2\[0\]\" to destination pin \"b2\[3\]\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a2\[0\] 1 PIN PIN_81 13 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 13; PIN Node = 'a2\[0\]'" {  } { { "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "" { Report "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "Compiler" "seg7_b" "UNKNOWN" "V1" "F:/实验及报告/电子测量实验/课件/数电/seg7_b/db/seg7_b.quartus_db" { Floorplan "F:/实验及报告/电子测量实验/课件/数电/seg7_b/" "" "" { a2[0] } "NODE_NAME" } "" } } { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns seg7:comp1\|b1_out\[3\]~1007 2 COMB LC6 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC6; Fanout = 1; COMB Node = 'seg7:comp1\|b1_out\[3\]~1007'" {  } { { "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "" { Report "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "Compiler" "seg7_b" "UNKNOWN" "V1" "F:/实验及报告/电子测量实验/课件/数电/seg7_b/db/seg7_b.quartus_db" { Floorplan "F:/实验及报告/电子测量实验/课件/数电/seg7_b/" "" "9.000 ns" { a2[0] seg7:comp1|b1_out[3]~1007 } "NODE_NAME" } "" } } { "Vhdl1.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/Vhdl1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns b2\[3\] 3 PIN PIN_10 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'b2\[3\]'" {  } { { "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "" { Report "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "Compiler" "seg7_b" "UNKNOWN" "V1" "F:/实验及报告/电子测量实验/课件/数电/seg7_b/db/seg7_b.quartus_db" { Floorplan "F:/实验及报告/电子测量实验/课件/数电/seg7_b/" "" "4.000 ns" { seg7:comp1|b1_out[3]~1007 b2[3] } "NODE_NAME" } "" } } { "seg7_b.vhd" "" { Text "F:/实验及报告/电子测量实验/课件/数电/seg7_b/seg7_b.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns ( 86.67 % ) " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 13.33 % ) " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "" { Report "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Report_Window_01.qrpt" "Compiler" "seg7_b" "UNKNOWN" "V1" "F:/实验及报告/电子测量实验/课件/数电/seg7_b/db/seg7_b.quartus_db" { Floorplan "F:/实验及报告/电子测量实验/课件/数电/seg7_b/" "" "15.000 ns" { a2[0] seg7:comp1|b1_out[3]~1007 b2[3] } "NODE_NAME" } "" } } { "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/downloads/altera.quartus.ii.v5.1-zwtiso/out come/bin/Technology_Viewer.qrui" "15.000 ns" { a2[0] a2[0]~out seg7:comp1|b1_out[3]~1007 b2[3] } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 4.000ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 06 17:18:29 2006 " "Info: Processing ended: Thu Apr 06 17:18:29 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}