seg7_b.fit.summary

这是一个用VHDL语言编写的数字电路程序

Fitter Status : Successful - Thu Apr 06 17:18:24 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : seg7_b
Top-level Entity Name : seg7_b
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Total macrocells : 17 / 128 ( 13 % )
Total pins : 25 / 68 ( 37 % )