seg7_b.vhd

来自「这是一个用VHDL语言编写的数字电路程序」· VHDL 代码 · 共 20 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity seg7_b is
  Port(a2: in std_logic_vector(3 downto 0);
       c2: out std_logic_vector(3 downto 0);
       b2: out std_logic_vector(6 downto 0);
       catn: out std_logic_vector(5 downto 0));
end seg7_b;
architecture seg7_arch of seg7_b is
 component seg7
   port(a1_in:in std_logic_vector(3 downto 0);
        b1_out:out std_logic_vector(6 downto 0));
 end component;
  begin 
   c2<=a2;
   catn<="111110";
comp1:seg7 port map(a2,b2);
end seg7_arch;