seg7_b.map.summary

这是一个用VHDL语言编写的数字电路程序

Analysis & Synthesis Status : Successful - Thu Apr 06 17:18:22 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : seg7_b
Top-level Entity Name : seg7_b
Family : MAX7000S
Total macrocells : 17
Total pins : 21