vhdl1.vhd

来自「这是一个用VHDL语言编写的数字电路程序」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seg7 is
 port(a1_in:in std_logic_vector(3 downto 0);
      b1_out:out std_logic_vector(6 downto 0));
end seg7;
architecture seg7_arch of seg7 is
begin
process(a1_in)
   begin
   case a1_in is
    when "0000"=> b1_out <="1111110";--0
    when "0001"=> b1_out <="0110000";--1
    when "0010"=> b1_out <="1101101";--2
    when "0011"=> b1_out <="1111001";--3
    when "0100"=> b1_out <="0110011";--4
    when "0101"=> b1_out <="1011011";--5
    when "0110"=> b1_out <="1011111";--6
    when "0111"=> b1_out <="1110000";--7
    when "1000"=> b1_out <="1111111";--8
    when "1001"=> b1_out <="1111011";--9
    when others=> b1_out <="0000000";--X
end case;
end process;
end seg7_arch;