item_new2.fit.rpt

项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号

+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                         ;
+-----------------------------------------------------------------------------+-----------------+
; Name                                                                        ; Value           ;
+-----------------------------------------------------------------------------+-----------------+
; Mid Wire Use - Fit Attempt 1                                                ; 64              ;
; Mid Slack - Fit Attempt 1                                                   ; -15134          ;
; Internal Atom Count - Fit Attempt 1                                         ; 158             ;
; LE/ALM Count - Fit Attempt 1                                                ; 158             ;
; LAB Count - Fit Attempt 1                                                   ; 17              ;
; Outputs per Lab - Fit Attempt 1                                             ; 5.765           ;
; Inputs per LAB - Fit Attempt 1                                              ; 9.176           ;
; Global Inputs per LAB - Fit Attempt 1                                       ; 1.706           ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1    ; 0:14;1:3        ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                             ; 0:7;1:3;2:7     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                        ; 0:2;1:5;2:7;3:3 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                       ; 0:2;1:6;2:6;3:3 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                 ; 1:6;2:7;3:4     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                  ; 1:7;2:6;3:4     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1        ; 0:9;1:8         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1          ; 0:16;1:1        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:6;1:9;2:2     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                     ; 1:6;2:9;3:2     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                 ; 1:6;2:11        ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1            ; 0:15;1:2        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                            ; 1:10;2:7        ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                          ; 0:10;1:7        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                        ; 1:17            ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                   ; 0:11;1:6        ;
; LEs in Chains - Fit Attempt 1                                               ; 66              ;
; LEs in Long Chains - Fit Attempt 1                                          ; 42              ;
; LABs with Chains - Fit Attempt 1                                            ; 9               ;
; LABs with Multiple Chains - Fit Attempt 1                                   ; 0               ;
; Time - Fit Attempt 1                                                        ; 1               ;
; Time in tsm_tan.dll - Fit Attempt 1                                         ; 0.032           ;
+-----------------------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Early Slack - Fit Attempt 1         ; -17063 ;
; Mid Wire Use - Fit Attempt 1        ; 16     ;
; Mid Slack - Fit Attempt 1           ; -16111 ;
; Late Wire Use - Fit Attempt 1       ; 17     ;
; Late Slack - Fit Attempt 1          ; -16016 ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_dat.dll - Fit Attempt 1 ; 0.157  ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.265  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -15834 ;
; Early Wire Use - Fit Attempt 1      ; 14     ;
; Peak Regional Wire - Fit Attempt 1  ; 13     ;
; Mid Slack - Fit Attempt 1           ; -16244 ;
; Late Slack - Fit Attempt 1          ; -15839 ;
; Late Slack - Fit Attempt 1          ; -15839 ;
; Late Wire Use - Fit Attempt 1       ; 20     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.140  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Fri Aug 22 14:34:23 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off item_new2 -c item_new2
Info: Selected device EPM240T100C5 for design "item_new2"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clkin" to use Global clock in PIN 12
Info: Automatically promoted signal "ain" to use Global clock
Info: Pin "ain" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "bin" to use Global clock
Info: Pin "bin" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted signal "itemnew3_2:u1|once" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to pin delay of 10.479 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y4; Fanout = 1; REG Node = 'itemnew3_2:u1|num_clk[10]'
    Info: 2: + IC(0.693 ns) + CELL(0.740 ns) = 1.433 ns; Loc. = LAB_X6_Y4; Fanout = 1; COMB Node = 'data~557'
    Info: 3: + IC(1.056 ns) + CELL(0.200 ns) = 2.689 ns; Loc. = LAB_X6_Y4; Fanout = 1; COMB Node = 'data~558'
    Info: 4: + IC(2.291 ns) + CELL(0.200 ns) = 5.180 ns; Loc. = LAB_X7_Y3; Fanout = 1; COMB Node = 'data~559'
    Info: 5: + IC(0.342 ns) + CELL(0.914 ns) = 6.436 ns; Loc. = LAB_X7_Y3; Fanout = 1; COMB Node = 'data~560'
    Info: 6: + IC(1.721 ns) + CELL(2.322 ns) = 10.479 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'data[2]'
    Info: Total cell delay = 4.376 ns ( 41.76 % )
    Info: Total interconnect delay = 6.103 ns ( 58.24 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 12% of the available device resources. Peak interconnect usage is 12%
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Aug 22 14:34:27 2008
    Info: Elapsed time: 00:00:05