itemnew3_2.vhd

项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY itemnew3_2 IS
	PORT
	(
		a,clk	: IN	STD_LOGIC;
		num_a	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		num_clk : OUT	STD_LOGIC_VECTOR(20 DOWNTO 0);
		int0	: OUT   STD_LOGIC
	);
END itemnew3_2;
ARCHITECTURE a OF itemnew3_2 IS
	SIGNAL num_clk_s : STD_LOGIC_VECTOR(20 DOWNTO 0);
	SIGNAL num_a_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal once,once_1	:std_logic;
BEGIN

p_a:PROCESS (a,clk)
BEGIN
if a'event and a='1' then num_a_s<=num_a_s+1;end if;
if clk'event and clk='1' then num_clk_s<=num_clk_s+1;end if;
if once='1' then num_clk_s<="000000000000000000000";
num_a_s<="00000001";once_1<='0';
else once_1<='1';end if;
END PROCESS p_a;

p_b:PROCESS(num_clk_s,a)
	VARIABLE lastone	: STD_LOGIC:='0';
BEGIN
	if a'event and a='1' and lastone='1' then 
	num_clk<=num_clk_s;
	num_a<=num_a_s;
	once<='1';
	lastone:='0';
	end if;
	if num_clk_s = "100100001011110110010" then lastone:='1';end if;
	if once_1='0' then once<='0';end if;
END PROCESS p_b;
int0<=once;

END a;