item_new2.fit.talkback.xml

项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号

<output_pins>
	<row>
		<name>data[0]</name>
		<pin__>75</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>yes</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[1]</name>
		<pin__>74</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[2]</name>
		<pin__>73</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[3]</name>
		<pin__>72</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[4]</name>
		<pin__>71</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>3</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[5]</name>
		<pin__>70</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>4</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>yes</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[6]</name>
		<pin__>69</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>data[7]</name>
		<pin__>68</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>yes</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
	<row>
		<name>intermit</name>
		<pin__>50</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>16mA</current_strength>
		<fast_output_connection>no</fast_output_connection>
		<location_assigned_by>User</location_assigned_by>
		<load units="pF">10</load>
	</row>
</output_pins>
<i_o_bank_usage>
	<row>
		<i_o_bank>1</i_o_bank>
		<usage>3 / 38 ( 8 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>2</i_o_bank>
		<usage>12 / 42 ( 29 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>64</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>-15134</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>158</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>158</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>17</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>5.765</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>9.176</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>1.706</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock / CE pair + async load&apos; - Fit Attempt 1</name>
		<value>0:14;1:3</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ce + sync load&apos; - Fit Attempt 1</name>
		<value>0:7;1:3;2:7</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:2;1:5;2:7;3:3</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route combination&apos; - Fit Attempt 1</name>
		<value>0:2;1:6;2:6;3:3</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global with asyn_clear&apos; - Fit Attempt 1</name>
		<value>1:6;2:7;3:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route with async_clear&apos; - Fit Attempt 1</name>
		<value>1:7;2:6;3:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global async clear + sync clear&apos; - Fit Attempt 1</name>
		<value>0:9;1:8</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock/non-asynch_clear&apos; - Fit Attempt 1</name>
		<value>0:16;1:1</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ygr_cl_ngclk_gclkce_sload_aload_constraint&apos; - Fit Attempt 1</name>
		<value>0:6;1:9;2:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global control signals&apos; - Fit Attempt 1</name>
		<value>1:6;2:9;3:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>1:6;2:11</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair with aload used&apos; - Fit Attempt 1</name>
		<value>0:15;1:2</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair&apos; - Fit Attempt 1</name>
		<value>1:10;2:7</value>
	</row>
	<row>
		<name>LAB Constraint &apos;sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:10;1:7</value>
	</row>
	<row>
		<name>LAB Constraint &apos;invert_a constraint&apos; - Fit Attempt 1</name>
		<value>1:17</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:11;1:6</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>66</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>42</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>9</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.032</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>7</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>-17063</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>16</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>-16111</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>17</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>-16016</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.157</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.265</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>-15834</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>14</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>13</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>-16244</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>-15839</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>-15839</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>20</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.140</value>
	</row>
</advanced_data___routing>
<compilation_summary>
	<flow_status>Successful - Fri Aug 22 14:34:27 2008</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>item_new2</revision_name>
	<top_level_entity_name>item_new2</top_level_entity_name>
	<family>MAX II</family>
	<device>EPM240T100C5</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>158 / 240 ( 66 % )</total_logic_elements>
	<total_pins>15 / 80 ( 19 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<ufm_blocks>0 / 1 ( 0 % )</ufm_blocks>
</compilation_summary>
<compile_id>95285F11</compile_id>
<files>
	<top>C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd</top>
	<extensions>
		<ext ext_name="vhd">2</ext>
	</extensions>
	<sub_files>
		<sub_file>C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2.vhd</sub_file>
		<sub_file>C:/Documents and Settings/Administrator/桌面/新建文件夹/itemnew3_2.vhd</sub_file>
	</sub_files>
</files>
<architecture>
	<family>MAX II</family>
	<auto_device>OFF</auto_device>
	<device>EPM240T100C5</device>
</architecture>
<pkg_io>
	<pin_std count="15">LVTTL</pin_std>
</pkg_io>
<research>
	<le_sclr>0</le_sclr>
	<le_aclr>130</le_aclr>
	<le_aload>16</le_aload>
	<le_sload>49</le_sload>
	<le_inverta>0</le_inverta>
	<le_carry_in>41</le_carry_in>
	<le_ce>62</le_ce>
	<le_clk>130</le_clk>
	<le_ce_sload>49</le_ce_sload>
	<pin_sclr>0</pin_sclr>
	<pin_aclr>0</pin_aclr>
	<pin_ce_in>0</pin_ce_in>
	<pin_ce_out>0</pin_ce_out>
</research>
</talkback>