item_new2.fit.talkback.xml

项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号

<!--
This XML file (created on Fri Aug 22 14:34:28 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>00e0a0048ea8</host_id>
	<nic_id>00e0a0048ea8</nic_id>
	<cdrive_id>70a18923</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_fit.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Fri Aug 22 14:34:28 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1808</cpu_freq>
	</cpu>
	<ram units="MB">512</ram>
</machine>
<top_file>C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2</top_file>
<resource_usage_summary>
	<rsc name="Total logic elements" util="66" max=" 240 " type="int">158 </rsc>
	<rsc name="-- Combinational with no register" type="int">28</rsc>
	<rsc name="-- Register only" type="int">24</rsc>
	<rsc name="-- Combinational with a register" type="int">106</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">48</rsc>
	<rsc name="-- 3 input functions" type="int">6</rsc>
	<rsc name="-- 2 input functions" type="int">68</rsc>
	<rsc name="-- 1 input functions" type="int">14</rsc>
	<rsc name="-- 0 input functions" type="int">22</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">97</rsc>
	<rsc name="-- arithmetic mode" type="int">61</rsc>
	<rsc name="-- qfbk mode" type="int">34</rsc>
	<rsc name="-- register cascade mode" type="int">0</rsc>
	<rsc name="-- synchronous clear/load mode" type="int">49</rsc>
	<rsc name="-- asynchronous clear/load mode" type="int">72</rsc>
	<rsc name="Total LABs" util="79" max=" 24 " type="int">19 </rsc>
	<rsc name="Logic elements in carry chains" type="int">66</rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="19" max=" 80 " type="int">15 </rsc>
	<rsc name="-- Clock pins" type="int">1</rsc>
	<rsc name="Global signals" type="int">4</rsc>
	<rsc name="UFM blocks" util="0" max=" 1 " type="int">0 </rsc>
	<rsc name="Global clocks" util="100" max=" 4 " type="int">4 </rsc>
	<rsc name="Maximum fan-out node" type="text">clkin</rsc>
	<rsc name="Maximum fan-out" type="int">50</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">itemnew3_2:u1|\p_b:lastone</rsc>
	<rsc name="Highest non-global fan-out" type="int">31</rsc>
	<rsc name="Total fan-out" type="int">692</rsc>
	<rsc name="Average fan-out" type="float">4.00</rsc>
</resource_usage_summary>
<control_signals>
	<row>
		<name>itemnew3_2:u1|once</name>
		<location>LC_X2_Y3_N4</location>
		<fan_out>31</fan_out>
		<usage>Async. clear, Async. load, Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK3</global_line_name>
	</row>
	<row>
		<name>itemnew3_2:u2|once</name>
		<location>LC_X7_Y2_N9</location>
		<fan_out>31</fan_out>
		<usage>Async. clear, Async. load, Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>ain</name>
		<location>PIN_97</location>
		<fan_out>39</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK1</global_line_name>
	</row>
	<row>
		<name>bin</name>
		<location>PIN_99</location>
		<fan_out>39</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK2</global_line_name>
	</row>
	<row>
		<name>clkin</name>
		<location>PIN_12</location>
		<fan_out>50</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK0</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>rtl~429</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>data~541</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>data~542</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>rtl~430</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>itemnew3_2:u2|num_clk[19]</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>data~543</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>itemnew3_2:u1|num_clk[16]</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>data~544</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>data~545</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>itemnew3_2:u2|num_a[0]</name>
		<fan_out>1</fan_out>
	</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
	<rsc name="Local interconnects" util="20" max=" 888 " type="int">177 </rsc>
	<rsc name="LUT chains" util="7" max=" 216 " type="int">16 </rsc>
	<rsc name="R4s" util="16" max=" 704 " type="int">111 </rsc>
	<rsc name="C4s" util="12" max=" 784 " type="int">91 </rsc>
	<rsc name="Global clocks" util="100" max=" 4 " type="int">4 </rsc>
	<rsc name="LAB clocks" util="50" max=" 32 " type="int">16 </rsc>
	<rsc name="Direct links" util="3" max=" 888 " type="int">31 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off item_new2 -c item_new2</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<info>Info: Quartus II Fitter was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:05</info>
	<info>Info: Processing ended: Fri Aug 22 14:34:27 2008</info>
	<info>Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design&apos;s timing and routability requirements required full optimization.</info>
	<info>Info: Fitter routing operations ending: elapsed time is 00:00:01</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EPM240T100C5</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Guarantee I/O Paths Have Zero Hold Time at Fast Corner</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform Physical Synthesis for Combinational Logic</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Asynchronous Signal Pipelining</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion - Logic Duplication</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Passive Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>ain</name>
		<pin__>97</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>3</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>39</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>bin</name>
		<pin__>99</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>2</x_coordinate>
		<y_coordinate>5</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>39</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>clkin</name>
		<pin__>12</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>1</x_coordinate>
		<y_coordinate>3</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>50</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>yes</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>sel[0]</name>
		<pin__>53</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>1</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>9</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>sel[1]</name>
		<pin__>52</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>1</y_coordinate>
		<cell_number>4</cell_number>
		<combinational_fan_out>6</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>sel[2]</name>
		<pin__>51</pin__>
		<i_o_bank>1</i_o_bank>
		<x_coordinate>7</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>9</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<location_assigned_by>User</location_assigned_by>
	</row>
</input_pins>