item_new2.tan.talkback.xml
来自「项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度」· XML 代码 · 共 116 行
XML
116 行
<!--
This XML file (created on Fri Aug 22 14:34:34 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
<host_id>00e0a0048ea8</host_id>
<nic_id>00e0a0048ea8</nic_id>
<cdrive_id>70a18923</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 176</build>
<binary_type>32</binary_type>
<module>quartus_tan.exe</module>
<edition>Full Version</edition>
<compilation_end_time>Fri Aug 22 14:34:35 2008</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">1808</cpu_freq>
</cpu>
<ram units="MB">512</ram>
</machine>
<top_file>C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2</top_file>
<mep_data>
<command_line>quartus_tan --read_settings_files=off --write_settings_files=off item_new2 -c item_new2</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
<info>Info: Elapsed time: 00:00:01</info>
<info>Info: Processing ended: Fri Aug 22 14:34:34 2008</info>
<info>Info: Longest tpd from source pin "sel[0]" to destination pin "data[2]" is 15.140 ns</info>
<info>Info: Total interconnect delay = 9.432 ns ( 62.30 % )</info>
</messages>
<clock_settings_summary>
<row>
<clock_node_name>bin</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>clkin</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
<row>
<clock_node_name>ain</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
</clock_settings_summary>
<performance>
<nonclk>
<type>Worst-case tco</type>
<slack>N/A</slack>
<required>None</required>
<actual>15.818 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case tpd</type>
<slack>N/A</slack>
<required>None</required>
<actual>15.140 ns</actual>
</nonclk>
<clk>
<name>clkin</name>
<slack>N/A</slack>
<required>None</required>
<actual>178.95 MHz ( period = 5.588 ns )</actual>
</clk>
<clk>
<name>bin</name>
<slack>N/A</slack>
<required>None</required>
<actual>218.10 MHz ( period = 4.585 ns )</actual>
</clk>
<clk>
<name>ain</name>
<slack>N/A</slack>
<required>None</required>
<actual>222.82 MHz ( period = 4.488 ns )</actual>
</clk>
</performance>
<compile_id>45F879EF</compile_id>
</talkback>
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