📄 item_new2.map.talkback.xml
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<!--
This XML file (created on Fri Aug 22 14:34:20 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
<host_id>00e0a0048ea8</host_id>
<nic_id>00e0a0048ea8</nic_id>
<cdrive_id>70a18923</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 176</build>
<binary_type>32</binary_type>
<module>quartus_map.exe</module>
<edition>Full Version</edition>
<compilation_end_time>Fri Aug 22 14:34:21 2008</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">1808</cpu_freq>
</cpu>
<ram units="MB">512</ram>
</machine>
<top_file>C:/Documents and Settings/Administrator/桌面/新建文件夹/item_new2</top_file>
<eda_tools>
<eda_tool type="eda_design_synthesis">Design Compiler</eda_tool>
<eda_tool type="eda_simulation">ModelSim (VHDL)</eda_tool>
<eda_tool type="eda_timing_analysis">PrimeTime (VHDL)</eda_tool>
</eda_tools>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off item_new2 -c item_new2</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning (10492): VHDL Process Statement warning at itemnew3_2.vhd(39): signal "once_1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<warning>Warning (10492): VHDL Process Statement warning at itemnew3_2.vhd(24): signal "once" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<warning>Warning: Using design file itemnew3_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings</info>
<info>Info: Elapsed time: 00:00:04</info>
<info>Info: Processing ended: Fri Aug 22 14:34:20 2008</info>
<info>Info: Implemented 207 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 192 logic cells</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Device</option>
<setting>EPM240T100C5</setting>
</row>
<row>
<option>Top-level entity name</option>
<setting>item_new2</setting>
<default_value>item_new2</default_value>
</row>
<row>
<option>Family name</option>
<setting>MAX II</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Type of Retiming Performed During Resynthesis</option>
<setting>Full</setting>
</row>
<row>
<option>Resynthesis Optimization Effort</option>
<setting>Normal</setting>
</row>
<row>
<option>Physical Synthesis Level for Resynthesis</option>
<setting>Normal</setting>
</row>
<row>
<option>Use Generated Physical Constraints File</option>
<setting>On</setting>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Restructure Multiplexers</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- MAX II</option>
<setting>Balanced</setting>
<default_value>Balanced</default_value>
</row>
<row>
<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
<setting>70</setting>
<default_value>70</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Perform WYSIWYG Primitive Resynthesis</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform gate-level register retiming</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Shift Register Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Allow Synchronous Control Signals</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Force Use of Synchronous Clear Signals</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto RAM Block Balancing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Maximum Number of M512 Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Maximum Number of M4K Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Maximum Number of M-RAM Memory Blocks</option>
<setting>-1</setting>
<default_value>-1</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore Maximum Fan-Out Assignments</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Retiming Meta-Stability Register Sequence Length</option>
<setting>2</setting>
<default_value>2</default_value>
</row>
<row>
<option>PowerPlay Power Optimization</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>HDL message level</option>
<setting>Level2</setting>
<default_value>Level2</default_value>
</row>
</analysis___synthesis_settings>
<general_register_statistics>
<row>
<statistic>Total registers</statistic>
<value>130</value>
</row>
<row>
<statistic>Number of registers using Synchronous Clear</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Synchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Clear</statistic>
<value>56</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Load</statistic>
<value>16</value>
</row>
<row>
<statistic>Number of registers using Clock Enable</statistic>
<value>62</value>
</row>
<row>
<statistic>Number of registers using Preset</statistic>
<value>0</value>
</row>
</general_register_statistics>
<compilation_summary>
<flow_status>Successful - Fri Aug 22 14:34:20 2008</flow_status>
<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
<revision_name>item_new2</revision_name>
<top_level_entity_name>item_new2</top_level_entity_name>
<family>MAX II</family>
<device>EPM240T100C5</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>192</total_logic_elements>
<total_pins>15</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<ufm_blocks>0</ufm_blocks>
</compilation_summary>
<compile_id>9A551F04</compile_id>
</talkback>
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