📄 复件 (5) cnt_test.txt

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entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;

entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;

entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;

entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;

entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;

entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;



entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
 if clk'event and clk='1' then
	dm<=dm+1;
end if;
dout<=dm;
end process;
end cnt_arc;


entity cnt is
port(clk:in std_logic;
	din:in std_logic_vector(3 downto 0);
	dout:out std_logic_vector(3 downto 0));
end cnt;
architecture cnt_arc of cnt is
signal dm:std_logic_vector(3 downto 0);
begin
process(clk)
begin
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💿 文件大小 4 K
👤 上传用户 woshishenb
📂 所属分类 VHDL/FPGA/Verilog
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