key_matix44.map.rpt

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

; key_matrix44.bdf                 ; yes             ; Other           ; D:/My_eda/key_matix44/key_matrix44.bdf ;
+----------------------------------+-----------------+-----------------+----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 63    ;
;     -- Combinational with no register       ; 37    ;
;     -- Register only                        ; 14    ;
;     -- Combinational with a register        ; 12    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 16    ;
;     -- 3 input functions                    ; 5     ;
;     -- 2 input functions                    ; 27    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 45    ;
;     -- arithmetic mode                      ; 18    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 26    ;
; Total logic cells in carry chains           ; 19    ;
; I/O pins                                    ; 11    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 22    ;
; Total fan-out                               ; 177   ;
; Average fan-out                             ; 2.39  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                  ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+--------------+
; |key_matrix44              ; 63 (0)      ; 26           ; 0           ; 11   ; 0            ; 37 (0)       ; 14 (0)            ; 12 (0)           ; 19 (0)          ; 0 (0)      ; |key_matrix44                      ; work         ;
;    |clk_gen:inst1|         ; 49 (49)     ; 20           ; 0           ; 0    ; 0            ; 29 (29)      ; 12 (12)           ; 8 (8)            ; 19 (19)         ; 0 (0)      ; |key_matrix44|clk_gen:inst1        ; work         ;
;    |keydecoder_deb:inst2|  ; 10 (10)     ; 2            ; 0           ; 0    ; 0            ; 8 (8)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |key_matrix44|keydecoder_deb:inst2 ; work         ;
;    |keysan:inst|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |key_matrix44|keysan:inst          ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                     ;
+----------------------------------------------------+---------------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal       ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------------+------------------------+
; keydecoder_deb:inst2|functionkey                   ; keydecoder_deb:inst2|Mux0 ; yes                    ;
; keydecoder_deb:inst2|keyvalue[0]                   ; keydecoder_deb:inst2|Mux0 ; yes                    ;
; Number of user-specified and inferred latches = 2  ;                           ;                        ;
+----------------------------------------------------+---------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Fri Dec 05 12:41:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key_matix44 -c key_matix44
Info: Found 2 design units, including 1 entities, in source file keysan.vhd
    Info: Found design unit 1: keysan-behavier
    Info: Found entity 1: keysan
Info: Found 2 design units, including 1 entities, in source file clk_gen.vhd
    Info: Found design unit 1: clk_gen-rtl
    Info: Found entity 1: clk_gen
Info: Found 2 design units, including 1 entities, in source file keydecoder.vhd
    Info: Found design unit 1: keydecoder_deb-rtl
    Info: Found entity 1: keydecoder_deb
Warning: Can't analyze file -- file D:/My_eda/key_matix44/key_matix44.bdf is missing
Warning: Using design file key_matrix44.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: key_matrix44
Info: Elaborating entity "key_matrix44" for the top level hierarchy
Info: Elaborating entity "keydecoder_deb" for hierarchy "keydecoder_deb:inst2"
Warning (10036): Verilog HDL or VHDL warning at keydecoder.vhd(19): object "keypressed_asy" assigned a value but never read
Warning (10631): VHDL Process Statement warning at keydecoder.vhd(22): inferring latch(es) for signal or variable "keyvalue", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at keydecoder.vhd(22): inferring latch(es) for signal or variable "functionkey", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(84): signal "q1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(84): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(84): signal "q3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(84): signal "q4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(92): signal "q5" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at keydecoder.vhd(92): signal "q6" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info (10041): Inferred latch for "functionkey" at keydecoder.vhd(22)
Info (10041): Inferred latch for "keyvalue[0]" at keydecoder.vhd(22)
Info (10041): Inferred latch for "keyvalue[1]" at keydecoder.vhd(22)
Info (10041): Inferred latch for "keyvalue[2]" at keydecoder.vhd(22)
Info (10041): Inferred latch for "keyvalue[3]" at keydecoder.vhd(22)
Info: Elaborating entity "clk_gen" for hierarchy "clk_gen:inst1"
Info: Elaborating entity "keysan" for hierarchy "keysan:inst"
Warning: Latch keydecoder_deb:inst2|functionkey has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal keysan:inst|present_state[1]
Warning: Latch keydecoder_deb:inst2|keyvalue[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal key_in[0]
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "key_value[3]" is stuck at GND
    Warning (13410): Pin "key_value[2]" is stuck at GND
    Warning (13410): Pin "key_value[1]" is stuck at GND
Info: Implemented 74 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 6 output pins
    Info: Implemented 63 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
    Info: Peak virtual memory: 178 megabytes
    Info: Processing ended: Fri Dec 05 12:41:11 2008
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:04