prev_cmp_key_matix44.tan.qmsg

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

{ "Info" "ITDB_TSU_RESULT" "keydecoder_deb:inst2\|q5 key_in\[3\] clk 3.085 ns register " "Info: tsu for register \"keydecoder_deb:inst2\|q5\" (data pin = \"key_in\[3\]\", clock pin = \"clk\") is 3.085 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.002 ns + Longest pin register " "Info: + Longest pin to register delay is 6.002 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns key_in\[3\] 1 CLK PIN_74 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_74; Fanout = 1; CLK Node = 'key_in\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_in[3] } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.312 ns) + CELL(0.292 ns) 5.079 ns keydecoder_deb:inst2\|Mux0~732 2 COMB LC_X6_Y19_N4 3 " "Info: 2: + IC(3.312 ns) + CELL(0.292 ns) = 5.079 ns; Loc. = LC_X6_Y19_N4; Fanout = 3; COMB Node = 'keydecoder_deb:inst2\|Mux0~732'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.604 ns" { key_in[3] keydecoder_deb:inst2|Mux0~732 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.478 ns) 6.002 ns keydecoder_deb:inst2\|q5 3 REG LC_X6_Y19_N5 2 " "Info: 3: + IC(0.445 ns) + CELL(0.478 ns) = 6.002 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; REG Node = 'keydecoder_deb:inst2\|q5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.923 ns" { keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.245 ns ( 37.40 % ) " "Info: Total cell delay = 2.245 ns ( 37.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.757 ns ( 62.60 % ) " "Info: Total interconnect delay = 3.757 ns ( 62.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.002 ns" { key_in[3] keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.002 ns" { key_in[3] {} key_in[3]~out0 {} keydecoder_deb:inst2|Mux0~732 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 3.312ns 0.445ns } { 0.000ns 1.475ns 0.292ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns keydecoder_deb:inst2\|q5 2 REG LC_X6_Y19_N5 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; REG Node = 'keydecoder_deb:inst2\|q5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.002 ns" { key_in[3] keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.002 ns" { key_in[3] {} key_in[3]~out0 {} keydecoder_deb:inst2|Mux0~732 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 3.312ns 0.445ns } { 0.000ns 1.475ns 0.292ns 0.478ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk key_value\[0\] keydecoder_deb:inst2\|keyvalue\[0\] 22.451 ns register " "Info: tco from clock \"clk\" to destination pin \"key_value\[0\]\" through register \"keydecoder_deb:inst2\|keyvalue\[0\]\" is 22.451 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 16.451 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 16.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns clk_gen:inst1\|clk_scan 2 REG LC_X26_Y16_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X26_Y16_N4; Fanout = 4; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.780 ns) + CELL(0.935 ns) 8.901 ns keysan:inst\|present_state\[1\] 3 REG LC_X6_Y19_N2 8 " "Info: 3: + IC(4.780 ns) + CELL(0.935 ns) = 8.901 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.715 ns" { clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.590 ns) 10.125 ns keydecoder_deb:inst2\|Mux0~733 4 COMB LC_X6_Y19_N1 2 " "Info: 4: + IC(0.634 ns) + CELL(0.590 ns) = 10.125 ns; Loc. = LC_X6_Y19_N1; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~733'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 10.665 ns keydecoder_deb:inst2\|Mux0~734 5 COMB LC_X6_Y19_N5 2 " "Info: 5: + IC(0.426 ns) + CELL(0.114 ns) = 10.665 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~734'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.540 ns" { keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.672 ns) + CELL(0.114 ns) 16.451 ns keydecoder_deb:inst2\|keyvalue\[0\] 6 REG LC_X26_Y10_N9 1 " "Info: 6: + IC(5.672 ns) + CELL(0.114 ns) = 16.451 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.786 ns" { keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.157 ns ( 25.27 % ) " "Info: Total cell delay = 4.157 ns ( 25.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.294 ns ( 74.73 % ) " "Info: Total interconnect delay = 12.294 ns ( 74.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.451 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.451 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.672ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register pin " "Info: + Longest register to pin delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keydecoder_deb:inst2\|keyvalue\[0\] 1 REG LC_X26_Y10_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.876 ns) + CELL(2.124 ns) 6.000 ns key_value\[0\] 2 PIN PIN_23 0 " "Info: 2: + IC(3.876 ns) + CELL(2.124 ns) = 6.000 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'key_value\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { keydecoder_deb:inst2|keyvalue[0] key_value[0] } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 64 736 912 80 "key_value\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 35.40 % ) " "Info: Total cell delay = 2.124 ns ( 35.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.876 ns ( 64.60 % ) " "Info: Total interconnect delay = 3.876 ns ( 64.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { keydecoder_deb:inst2|keyvalue[0] key_value[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { keydecoder_deb:inst2|keyvalue[0] {} key_value[0] {} } { 0.000ns 3.876ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.451 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.451 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.672ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.114ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { keydecoder_deb:inst2|keyvalue[0] key_value[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { keydecoder_deb:inst2|keyvalue[0] {} key_value[0] {} } { 0.000ns 3.876ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "keydecoder_deb:inst2\|keyvalue\[0\] key_in\[2\] clk 8.813 ns register " "Info: th for register \"keydecoder_deb:inst2\|keyvalue\[0\]\" (data pin = \"key_in\[2\]\", clock pin = \"clk\") is 8.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.451 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 16.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns clk_gen:inst1\|clk_scan 2 REG LC_X26_Y16_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X26_Y16_N4; Fanout = 4; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.780 ns) + CELL(0.935 ns) 8.901 ns keysan:inst\|present_state\[1\] 3 REG LC_X6_Y19_N2 8 " "Info: 3: + IC(4.780 ns) + CELL(0.935 ns) = 8.901 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.715 ns" { clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.590 ns) 10.125 ns keydecoder_deb:inst2\|Mux0~733 4 COMB LC_X6_Y19_N1 2 " "Info: 4: + IC(0.634 ns) + CELL(0.590 ns) = 10.125 ns; Loc. = LC_X6_Y19_N1; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~733'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 10.665 ns keydecoder_deb:inst2\|Mux0~734 5 COMB LC_X6_Y19_N5 2 " "Info: 5: + IC(0.426 ns) + CELL(0.114 ns) = 10.665 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~734'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.540 ns" { keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.672 ns) + CELL(0.114 ns) 16.451 ns keydecoder_deb:inst2\|keyvalue\[0\] 6 REG LC_X26_Y10_N9 1 " "Info: 6: + IC(5.672 ns) + CELL(0.114 ns) = 16.451 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.786 ns" { keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.157 ns ( 25.27 % ) " "Info: Total cell delay = 4.157 ns ( 25.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.294 ns ( 74.73 % ) " "Info: Total interconnect delay = 12.294 ns ( 74.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.451 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.451 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.672ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.638 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.638 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_in\[2\] 1 CLK PIN_4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_4; Fanout = 1; CLK Node = 'key_in\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_in[2] } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.442 ns) 3.388 ns keydecoder_deb:inst2\|Mux0~732 2 COMB LC_X6_Y19_N4 3 " "Info: 2: + IC(1.477 ns) + CELL(0.442 ns) = 3.388 ns; Loc. = LC_X6_Y19_N4; Fanout = 3; COMB Node = 'keydecoder_deb:inst2\|Mux0~732'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.919 ns" { key_in[2] keydecoder_deb:inst2|Mux0~732 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.808 ns) + CELL(0.442 ns) 7.638 ns keydecoder_deb:inst2\|keyvalue\[0\] 3 REG LC_X26_Y10_N9 1 " "Info: 3: + IC(3.808 ns) + CELL(0.442 ns) = 7.638 ns; Loc. = LC_X26_Y10_N9; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|keyvalue\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.250 ns" { keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.353 ns ( 30.81 % ) " "Info: Total cell delay = 2.353 ns ( 30.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.285 ns ( 69.19 % ) " "Info: Total interconnect delay = 5.285 ns ( 69.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.638 ns" { key_in[2] keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.638 ns" { key_in[2] {} key_in[2]~out0 {} keydecoder_deb:inst2|Mux0~732 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 1.477ns 3.808ns } { 0.000ns 1.469ns 0.442ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.451 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.451 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.672ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.114ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.638 ns" { key_in[2] keydecoder_deb:inst2|Mux0~732 keydecoder_deb:inst2|keyvalue[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.638 ns" { key_in[2] {} key_in[2]~out0 {} keydecoder_deb:inst2|Mux0~732 {} keydecoder_deb:inst2|keyvalue[0] {} } { 0.000ns 0.000ns 1.477ns 3.808ns } { 0.000ns 1.469ns 0.442ns 0.442ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}