prev_cmp_key_matix44.tan.qmsg

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register keysan:inst\|present_state\[1\] register keydecoder_deb:inst2\|q5 125.9 MHz 7.943 ns Internal " "Info: Clock \"clk\" has Internal fmax of 125.9 MHz between source register \"keysan:inst\|present_state\[1\]\" and destination register \"keydecoder_deb:inst2\|q5\" (period= 7.943 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.959 ns + Longest register register " "Info: + Longest register to register delay is 1.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keysan:inst\|present_state\[1\] 1 REG LC_X6_Y19_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.590 ns) 1.224 ns keydecoder_deb:inst2\|Mux0~733 2 COMB LC_X6_Y19_N1 2 " "Info: 2: + IC(0.634 ns) + CELL(0.590 ns) = 1.224 ns; Loc. = LC_X6_Y19_N1; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~733'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.309 ns) 1.959 ns keydecoder_deb:inst2\|q5 3 REG LC_X6_Y19_N5 2 " "Info: 3: + IC(0.426 ns) + CELL(0.309 ns) = 1.959 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; REG Node = 'keydecoder_deb:inst2\|q5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.899 ns ( 45.89 % ) " "Info: Total cell delay = 0.899 ns ( 45.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 54.11 % ) " "Info: Total interconnect delay = 1.060 ns ( 54.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.959 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.959 ns" { keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.634ns 0.426ns } { 0.000ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.723 ns - Smallest " "Info: - Smallest clock skew is -5.723 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns keydecoder_deb:inst2\|q5 2 REG LC_X6_Y19_N5 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; REG Node = 'keydecoder_deb:inst2\|q5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.677 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns clk_gen:inst1\|clk_scan 2 REG LC_X26_Y16_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X26_Y16_N4; Fanout = 4; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.780 ns) + CELL(0.711 ns) 8.677 ns keysan:inst\|present_state\[1\] 3 REG LC_X6_Y19_N2 8 " "Info: 3: + IC(4.780 ns) + CELL(0.711 ns) = 8.677 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.491 ns" { clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 35.90 % ) " "Info: Total cell delay = 3.115 ns ( 35.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.562 ns ( 64.10 % ) " "Info: Total interconnect delay = 5.562 ns ( 64.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.959 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.959 ns" { keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.634ns 0.426ns } { 0.000ns 0.590ns 0.309ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk keydecoder_deb:inst2|q5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} keydecoder_deb:inst2|q5 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 3 " "Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "keysan:inst\|present_state\[1\] keydecoder_deb:inst2\|functionkey clk 6.228 ns " "Info: Found hold time violation between source  pin or register \"keysan:inst\|present_state\[1\]\" and destination pin or register \"keydecoder_deb:inst2\|functionkey\" for clock \"clk\" (Hold time is 6.228 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.979 ns + Largest " "Info: + Largest clock skew is 7.979 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.656 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 16.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns clk_gen:inst1\|clk_scan 2 REG LC_X26_Y16_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X26_Y16_N4; Fanout = 4; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.780 ns) + CELL(0.935 ns) 8.901 ns keysan:inst\|present_state\[1\] 3 REG LC_X6_Y19_N2 8 " "Info: 3: + IC(4.780 ns) + CELL(0.935 ns) = 8.901 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.715 ns" { clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.590 ns) 10.125 ns keydecoder_deb:inst2\|Mux0~733 4 COMB LC_X6_Y19_N1 2 " "Info: 4: + IC(0.634 ns) + CELL(0.590 ns) = 10.125 ns; Loc. = LC_X6_Y19_N1; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~733'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.224 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 10.665 ns keydecoder_deb:inst2\|Mux0~734 5 COMB LC_X6_Y19_N5 2 " "Info: 5: + IC(0.426 ns) + CELL(0.114 ns) = 10.665 ns; Loc. = LC_X6_Y19_N5; Fanout = 2; COMB Node = 'keydecoder_deb:inst2\|Mux0~734'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.540 ns" { keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.699 ns) + CELL(0.292 ns) 16.656 ns keydecoder_deb:inst2\|functionkey 6 REG LC_X6_Y19_N7 1 " "Info: 6: + IC(5.699 ns) + CELL(0.292 ns) = 16.656 ns; Loc. = LC_X6_Y19_N7; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|functionkey'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.991 ns" { keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.335 ns ( 26.03 % ) " "Info: Total cell delay = 4.335 ns ( 26.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.321 ns ( 73.97 % ) " "Info: Total interconnect delay = 12.321 ns ( 73.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.656 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.656 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|functionkey {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.699ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.677 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 8.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns clk_gen:inst1\|clk_scan 2 REG LC_X26_Y16_N4 4 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X26_Y16_N4; Fanout = 4; REG Node = 'clk_gen:inst1\|clk_scan'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.717 ns" { clk clk_gen:inst1|clk_scan } "NODE_NAME" } } { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.780 ns) + CELL(0.711 ns) 8.677 ns keysan:inst\|present_state\[1\] 3 REG LC_X6_Y19_N2 8 " "Info: 3: + IC(4.780 ns) + CELL(0.711 ns) = 8.677 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.491 ns" { clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 35.90 % ) " "Info: Total cell delay = 3.115 ns ( 35.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.562 ns ( 64.10 % ) " "Info: Total interconnect delay = 5.562 ns ( 64.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.656 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.656 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|functionkey {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.699ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.292ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.527 ns - Shortest register register " "Info: - Shortest register to register delay is 1.527 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keysan:inst\|present_state\[1\] 1 REG LC_X6_Y19_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y19_N2; Fanout = 8; REG Node = 'keysan:inst\|present_state\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { keysan:inst|present_state[1] } "NODE_NAME" } } { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.590 ns) 1.231 ns keydecoder_deb:inst2\|Mux2~519 2 COMB LC_X6_Y19_N6 1 " "Info: 2: + IC(0.641 ns) + CELL(0.590 ns) = 1.231 ns; Loc. = LC_X6_Y19_N6; Fanout = 1; COMB Node = 'keydecoder_deb:inst2\|Mux2~519'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.231 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux2~519 } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.527 ns keydecoder_deb:inst2\|functionkey 3 REG LC_X6_Y19_N7 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.527 ns; Loc. = LC_X6_Y19_N7; Fanout = 1; REG Node = 'keydecoder_deb:inst2\|functionkey'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { keydecoder_deb:inst2|Mux2~519 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.704 ns ( 46.10 % ) " "Info: Total cell delay = 0.704 ns ( 46.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 53.90 % ) " "Info: Total interconnect delay = 0.823 ns ( 53.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux2~519 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.527 ns" { keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux2~519 {} keydecoder_deb:inst2|functionkey {} } { 0.000ns 0.641ns 0.182ns } { 0.000ns 0.590ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } } { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "16.656 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] keydecoder_deb:inst2|Mux0~733 keydecoder_deb:inst2|Mux0~734 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "16.656 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux0~733 {} keydecoder_deb:inst2|Mux0~734 {} keydecoder_deb:inst2|functionkey {} } { 0.000ns 0.000ns 0.782ns 4.780ns 0.634ns 0.426ns 5.699ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.114ns 0.292ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.677 ns" { clk clk_gen:inst1|clk_scan keysan:inst|present_state[1] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.677 ns" { clk {} clk~out0 {} clk_gen:inst1|clk_scan {} keysan:inst|present_state[1] {} } { 0.000ns 0.000ns 0.782ns 4.780ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { keysan:inst|present_state[1] keydecoder_deb:inst2|Mux2~519 keydecoder_deb:inst2|functionkey } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.527 ns" { keysan:inst|present_state[1] {} keydecoder_deb:inst2|Mux2~519 {} keydecoder_deb:inst2|functionkey {} } { 0.000ns 0.641ns 0.182ns } { 0.000ns 0.590ns 0.114ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}