prev_cmp_key_matix44.tan.qmsg

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|functionkey " "Warning: Node \"keydecoder_deb:inst2\|functionkey\" is a latch" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 12 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "keydecoder_deb:inst2\|keyvalue\[0\] " "Warning: Node \"keydecoder_deb:inst2\|keyvalue\[0\]\" is a latch" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 80 16 184 96 "clk" "" } } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "key_in\[1\] " "Info: Assuming node \"key_in\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "key_in\[3\] " "Info: Assuming node \"key_in\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "key_in\[2\] " "Info: Assuming node \"key_in\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "key_in\[0\] " "Info: Assuming node \"key_in\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "key_matrix44.bdf" "" { Schematic "D:/My_eda/key_matix44/key_matrix44.bdf" { { 16 16 184 32 "key_in\[3..0\]" "" } } } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "keydecoder_deb:inst2\|Mux0~734 " "Info: Detected gated clock \"keydecoder_deb:inst2\|Mux0~734\" as buffer" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keydecoder_deb:inst2\|Mux0~734" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_gen:inst1\|clk_scan " "Info: Detected ripple clock \"clk_gen:inst1\|clk_scan\" as buffer" {  } { { "clk_gen.vhd" "" { Text "D:/My_eda/key_matix44/clk_gen.vhd" 7 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_gen:inst1\|clk_scan" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keysan:inst\|present_state\[2\] " "Info: Detected ripple clock \"keysan:inst\|present_state\[2\]\" as buffer" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keysan:inst\|present_state\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keysan:inst\|present_state\[3\] " "Info: Detected ripple clock \"keysan:inst\|present_state\[3\]\" as buffer" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keysan:inst\|present_state\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keysan:inst\|present_state\[1\] " "Info: Detected ripple clock \"keysan:inst\|present_state\[1\]\" as buffer" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keysan:inst\|present_state\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "keysan:inst\|present_state\[0\] " "Info: Detected ripple clock \"keysan:inst\|present_state\[0\]\" as buffer" {  } { { "keysan.vhd" "" { Text "D:/My_eda/key_matix44/keysan.vhd" 18 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keysan:inst\|present_state\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "keydecoder_deb:inst2\|Mux0~732 " "Info: Detected gated clock \"keydecoder_deb:inst2\|Mux0~732\" as buffer" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keydecoder_deb:inst2\|Mux0~732" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "keydecoder_deb:inst2\|Mux0~733 " "Info: Detected gated clock \"keydecoder_deb:inst2\|Mux0~733\" as buffer" {  } { { "keydecoder.vhd" "" { Text "D:/My_eda/key_matix44/keydecoder.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "keydecoder_deb:inst2\|Mux0~733" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}