key_matrix44.vhd

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY key_matrix44 IS 
	port
	(
		clk :  IN  STD_LOGIC;
		key_in :  IN  STD_LOGIC_VECTOR(3 downto 0);
		key_pressed :  OUT  STD_LOGIC;
		key_function :  OUT  STD_LOGIC;
		key_value :  OUT  STD_LOGIC_VECTOR(3 downto 0)
	);
END key_matrix44;

ARCHITECTURE bdf_type OF key_matrix44 IS 

component keysan
	PORT(clk_scan : IN STD_LOGIC;
		 keydrv : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component clk_gen
	PORT(clk : IN STD_LOGIC;
		 clk_scan : OUT STD_LOGIC
	);
end component;

component keydecoder_deb
	PORT(clk : IN STD_LOGIC;
		 clk_scan : IN STD_LOGIC;
		 keydrv : IN STD_LOGIC_VECTOR(3 downto 0);
		 keyin : IN STD_LOGIC_VECTOR(3 downto 0);
		 keypressed : OUT STD_LOGIC;
		 functionkey : OUT STD_LOGIC;
		 keyvalue : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 downto 0);


BEGIN 



b2v_inst : keysan
PORT MAP(clk_scan => SYNTHESIZED_WIRE_3,
		 keydrv => SYNTHESIZED_WIRE_2);


b2v_inst1 : clk_gen
PORT MAP(clk => clk,
		 clk_scan => SYNTHESIZED_WIRE_3);


b2v_inst2 : keydecoder_deb
PORT MAP(clk => clk,
		 clk_scan => SYNTHESIZED_WIRE_3,
		 keydrv => SYNTHESIZED_WIRE_2,
		 keyin => key_in,
		 keypressed => key_pressed,
		 functionkey => key_function,
		 keyvalue => key_value);


END;