clk_gen.vhd.bak

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY clk_gen IS
PORT(
		clk		:IN STD_LOGIC;
		clk_scan:OUT STD_LOGIC
	);
END clk_gen;
ARCHITECTURE rtl OF clk_gen IS
SIGNAL cnt		:INTEGER RANGE 0 TO 499999;
BEGIN
	PROCESS(clk)
	BEGIN
		IF(clk'event and clk='1') THEN
			IF(cnt=cnt'high)THEN
				cnt<=0;
			ELSE
				cnt<=cnt+1;
			END IF;
		END IF;
	 END PROCESS
	PROCESS(cnt,clk)
	BEGIN
		IF(clk'event and clk='1') THEN
			IF (cnt>=cnt'high/2) THEN
				clk_scan<='1';
			ELSE
				clk_scan<='0';
			END IF;
		END IF;
	END PROCESS;
END rtl;