📄 altrfir32.mdl
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SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "21"
bwr "8"
Outputs "Signed Integer"
obwl "20"
obwr "0"
msb "20"
lsb "1"
rnd off
sat off
}
Block {
BlockType Reference
Name "Sync Delay"
Ports [1, 1]
Position [150, 283, 175, 327]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Memory Delay"
SourceType "ShiftTaps Altera Blockset"
bwaddr "1"
depth "13"
cst off
clken off
eab on
vDepthAltr "13"
}
Block {
BlockType Reference
Name "Sync Delay2"
Ports [1, 1]
Position [240, 274, 270, 336]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "VCC1"
Ports [0, 1]
Position [715, 237, 735, 253]
ForegroundColor "blue"
ShowName off
SourceBlock "bus_alteradspbuilder/VCC"
SourceType "SVCC AlteraBlockSet"
ncstsamp "FirSamplingPeriod"
}
Block {
BlockType Reference
Name "VCC2"
Ports [0, 1]
Position [465, 152, 485, 168]
ForegroundColor "blue"
ShowName off
SourceBlock "bus_alteradspbuilder/VCC"
SourceType "SVCC AlteraBlockSet"
ncstsamp "FirSamplingPeriod"
}
Block {
BlockType Reference
Name "res"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [1190, 247, 1255, 263]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "11"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "res"
nSgCpl "0"
}
Block {
BlockType Reference
Name "reset"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [65, 297, 130, 313]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "reset"
nSgCpl "0"
}
Block {
BlockType Outport
Name "Out[10:0]"
Position [1285, 248, 1315, 262]
ForegroundColor "blue"
}
Line {
SrcBlock "clr"
SrcPort 1
DstBlock "reset"
DstPort 1
}
Line {
SrcBlock "res"
SrcPort 1
DstBlock "Out[10:0]"
DstPort 1
}
Line {
SrcBlock "In[19:0]"
SrcPort 1
DstBlock "AltBus"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
DstBlock "Shift by Two"
DstPort 1
}
Line {
SrcBlock "Shift by Two"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
Points [0, 65]
DstBlock "BusConcatenation"
DstPort 1
}
Branch {
DstBlock "Goto"
DstPort 1
}
}
Line {
SrcBlock "VCC1"
SrcPort 1
DstBlock "Serial To Parallel"
DstPort 2
}
Line {
SrcBlock "Serial To Parallel"
SrcPort 1
DstBlock "BusConcatenation"
DstPort 2
}
Line {
SrcBlock "GND"
SrcPort 1
DstBlock "Serial To Parallel"
DstPort 3
}
Line {
SrcBlock "Delay4"
SrcPort 1
DstBlock "res"
DstPort 1
}
Line {
SrcBlock "GND1"
SrcPort 1
DstBlock "Delay4"
DstPort 3
}
Line {
SrcBlock "BusConcatenation"
SrcPort 1
DstBlock "Output Resolution\nArea of Interrest"
DstPort 1
}
Line {
SrcBlock "ExtractBit"
SrcPort 1
DstBlock "Serial To Parallel"
DstPort 1
}
Line {
SrcBlock "Reset On\nLast Partial Product"
SrcPort 1
Points [40, 0; 0, 45]
DstBlock "Adder"
DstPort 1
}
Line {
SrcBlock "GND2"
SrcPort 1
DstBlock "Reset On\nLast Partial Product"
DstPort 3
}
Line {
SrcBlock "reset"
SrcPort 1
DstBlock "Sync Delay"
DstPort 1
}
Line {
SrcBlock "From"
SrcPort 1
DstBlock "Reset On\nLast Partial Product"
DstPort 2
}
Line {
SrcBlock "From1"
SrcPort 1
DstBlock "Delay4"
DstPort 2
}
Line {
SrcBlock "From2"
SrcPort 1
DstBlock "Reset On\nLast Partial Product"
DstPort 1
}
Line {
SrcBlock "VCC2"
SrcPort 1
DstBlock "Adder"
DstPort 4
}
Line {
SrcBlock "Adder"
SrcPort 2
Points [5, 0]
Branch {
DstBlock "Delay"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "ExtractBit"
DstPort 1
}
}
Line {
SrcBlock "Sync Delay"
SrcPort 1
Points [35, 0]
Branch {
DstBlock "Sync Delay2"
DstPort 1
}
Branch {
Points [0, -50]
Branch {
Points [0, -45]
Branch {
DstBlock "BusBuild"
DstPort 2
}
Branch {
Points [0, -25]
DstBlock "BusBuild"
DstPort 1
}
}
Branch {
Points [225, 0; 0, -105]
DstBlock "Adder"
DstPort 3
}
}
}
Line {
SrcBlock "AltBus"
SrcPort 1
DstBlock "Pipeline \nDelay"
DstPort 1
}
Line {
SrcBlock "Inverse Last\nPartial Product"
SrcPort 1
Points [5, 0; 0, -30]
DstBlock "Adder"
DstPort 2
}
Line {
SrcBlock "Pipeline \nDelay"
SrcPort 1
DstBlock "Inverse Last\nPartial Product"
DstPort 1
}
Line {
SrcBlock "Sync Delay2"
SrcPort 1
DstBlock "Goto1"
DstPort 1
}
Line {
SrcBlock "Output Resolution\nArea of Interrest"
SrcPort 1
DstBlock "Delay4"
DstPort 1
}
Line {
SrcBlock "BusBuild"
SrcPort 1
Points [10, 0; 0, -25]
DstBlock "Inverse Last\nPartial Product"
DstPort 2
}
}
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [1275, 430, 1305, 465]
Location [227, 143, 706, 669]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
axes2 ""
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "Shift Taps"
Ports [1, 5]
Position [505, 123, 560, 197]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "4"
depth "8"
cst on
clken off
eab on
}
Block {
BlockType Reference
Name "Shift Taps1"
Ports [1, 9]
Position [505, 346, 560, 514]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "8"
depth "8"
cst on
clken off
eab on
}
Block {
BlockType Reference
Name "Shift Taps2"
Ports [1, 9]
Position [505, 551, 560, 719]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "8"
depth "8"
cst on
clken off
eab on
}
Block {
BlockType Reference
Name "Shift Taps4"
Ports [1, 5]
Position [505, 228, 560, 302]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "4"
depth "8"
cst on
clken off
eab on
}
Block {
BlockType Reference
Name "Shift Taps5"
Ports [1, 5]
Position [505, 753, 560, 827]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "4"
depth "8"
cst on
clken off
eab on
}
Block {
BlockType Reference
Name "Shift Taps6"
Ports [1, 4]
Position [505, 858, 560, 932]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Shift Taps"
SourceType "ShiftTaps Altera Blockset"
bwaddr "4"
depth "8"
cst off
clken off
eab on
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [149, 493, 218, 540]
ForegroundColor "blue"
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Cyclone"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "G:\\EDA\\Quartue_II\\DSP\\AltrFir32"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Global Buffer"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
}
Block {
BlockType Sin
Name "Sine Wave"
Position [25, 90, 55, 120]
SineType "Sample based"
Amplitude "100"
Samples "100"
SampleTime "8"
}
Block {
BlockType Reference
Name "Start"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [140, 207, 205, 223]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "8"
bwr "8"
sat off
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