crc_peripheral.v

采用nios2的嵌入式数字钟的设计与实现

// crc_peripheral.v
// Graham McKenzie 31 Oct 2003  (Modified to Verilog by A.Morris Dec 2003)

// Used for calculation of CRC16-CCITT
// Intended use is as custom peripheral for Nios processor

// When address is logic 0 =>
// Internal CRC register is initialised with write_data value

// When address is logic 1 =>
// CRC calulation is updated based on input word on write_data

// CRC result is obtained by reading any address



module crc_peripheral ( reset, clk, chipselect, write,
                        writedata, address, readdata);
                     
input         reset;
input         clk;
input         chipselect;
input         write;
input  [31:0] writedata;
input         address;
                      
output [31:0] readdata;


reg [15:0] crc_result;
reg [15:0] crc_reg;

//////////
// Set result output

assign readdata = {16'h0, crc_reg};
    
/////////
// Initialise or update CRC reg based on address line
                  
wire [15:0] crc_reg_input = (address) ? crc_result : writedata[15:0]; 

//////////
// CRC needs big endian data but Nios is little endian
// Convert data here
                     
wire [15:0] crc_word = {writedata[7:0], writedata[15:8]};
wire [15:0] next_crc_word = {writedata[23:16], writedata[31:24]};

/////////
// CRC calculation

integer    i;
reg [15:0] crc_array[0:16];

always @ (crc_reg, crc_word, next_crc_word)
begin
  crc_array[16] = crc_reg;
  for (i=15; i>=0; i=i-1) 
  begin
     crc_array [i][0]  = crc_array [i+1][15] ^ crc_word[i];
     crc_array [i][1]  = crc_array [i+1][0];
     crc_array [i][2]  = crc_array [i+1][1];
     crc_array [i][3]  = crc_array [i+1][2];
     crc_array [i][4]  = crc_array [i+1][3];
     crc_array [i][5]  = crc_array [i+1][4] ^ crc_array [i][0];
     crc_array [i][6]  = crc_array [i+1][5];
     crc_array [i][7]  = crc_array [i+1][6];
     crc_array [i][8]  = crc_array [i+1][7];
     crc_array [i][9]  = crc_array [i+1][8];
     crc_array [i][10] = crc_array [i+1][9];
     crc_array [i][11] = crc_array [i+1][10];
     crc_array [i][12] = crc_array [i+1][11] ^ crc_array [i][0];
     crc_array [i][13] = crc_array [i+1][12];
     crc_array [i][14] = crc_array [i+1][13];
     crc_array [i][15] = crc_array [i+1][14];
  end
	
  crc_array[16] = crc_array[0];
	
  for (i=15; i>=0; i=i-1) 
  begin
    crc_array [i][0] = crc_array [i+1][15] ^ next_crc_word[i];
    crc_array [i][1] = crc_array [i+1][0];
    crc_array [i][2] = crc_array [i+1][1];
    crc_array [i][3] = crc_array [i+1][2];
    crc_array [i][4] = crc_array [i+1][3];
    crc_array [i][5] = crc_array [i+1][4] ^ crc_array [i][0];
    crc_array [i][6] = crc_array [i+1][5];
    crc_array [i][7] = crc_array [i+1][6];
    crc_array [i][8] = crc_array [i+1][7];
    crc_array [i][9] = crc_array [i+1][8];
    crc_array [i][10] = crc_array [i+1][9];
    crc_array [i][11] = crc_array [i+1][10];
    crc_array [i][12] = crc_array [i+1][11] ^ crc_array [i][0];
    crc_array [i][13] = crc_array [i+1][12];
    crc_array [i][14] = crc_array [i+1][13];
    crc_array [i][15] = crc_array [i+1][14];
  end
	
  crc_result <= crc_array [0];
	
end

// CRC Register
always @ (posedge clk or posedge reset)
begin
  if (reset)
    crc_reg <= 0;
  else
    if (write && chipselect)
      crc_reg <= crc_reg_input;
end
		
endmodule