custominstruction_cpu.vhd

采用nios2的嵌入式数字钟的设计与实现

--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity custominstruction_cpu is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset : IN STD_LOGIC;
                 signal start : IN STD_LOGIC;

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity custominstruction_cpu;


architecture europa of custominstruction_cpu is
--synthesis read_comments_as_HDL on
--component crc is 
--           port (
--                 
--                    signal clk : IN STD_LOGIC;
--                    signal clk_en : IN STD_LOGIC;
--                    signal dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--                    signal datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
--                    signal reset : IN STD_LOGIC;
--                    signal start : IN STD_LOGIC;
--
--                 
--                    signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
--                 );
--end component crc;
--
--synthesis read_comments_as_HDL off
                signal internal_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --vhdl renameroo for output signals
  result <= internal_result;
--synthesis read_comments_as_HDL on
--    the_crc : crc
--      port map(
--        result => internal_result,
--        clk => clk,
--        clk_en => clk_en,
--        dataa => dataa,
--        datab => datab,
--        reset => reset,
--        start => start
--      );
--
--
--synthesis read_comments_as_HDL off

end europa;