📄 a1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity a1 is
PORT(
reset : in std_logic;
clk : in std_logic;
ad_clk : out std_logic;
TAEA : in std_logic_vector(5 downto 0);
TEAD : inout std_logic_vector(15 downto 0);
TEBD : inout std_logic_vector(15 downto 0);
TCE1 : in std_logic;
TCE2 : in std_logic;
TCE3 : in std_logic;
TEACLK : in std_logic;
TAARE : in std_logic;
TAAWE : in std_logic;
TEBCLK : in std_logic;
TBBWE : in std_logic;
TBCE1 : in std_logic;
TBCE2 : in std_logic;
TBBRE : in std_logic;
EMIFB_OE : out std_logic;
EMIFB_DIR : out std_logic;
EMIFA_OE : out std_logic;
EMIFA_DIR : out std_logic;
led : out std_logic_vector(7 downto 0);
------------AD1---------------------------------------
AD1_D : in std_logic_vector(11 downto 0);
AD1_DOR : in std_logic;
AD1_DCO : in std_logic;
------------AD2---------------------------------------
AD2_D : in std_logic_vector(11 downto 0);
AD2_DOR : in std_logic;
AD2_DCO : in std_logic;
gpio4 : in std_logic;
gpio5 : out std_logic; --束同步， fpga->dsp
gpio6 : out std_logic; --帧同步 fpga->dsp
gpio7 : out std_logic; --正半周 fifo aclr U1 fifo1
gpio9 : in std_logic; --负半周 fifo aclr U2 fifo2
gpio10 : in std_logic;
gpio11 : out std_logic;
gpio12 : out std_logic;
gpio13 : out std_logic;
eo1 : out std_logic;
eo2 : out std_logic;
eo3 : in std_logic;
eo4 : in std_logic;
eo5 : out std_logic;
eo6 : out std_logic;
eo7 : out std_logic;
eo8 : out std_logic;
eo9 : out std_logic;
eo10 : out std_logic;
eo11 : out std_logic;
eo12 : out std_logic;
eo13 : out std_logic;
eo14 : in std_logic;
eo15 : in std_logic;
eo16 : in std_logic;
eo17 : out std_logic;
eo18 : in std_logic;
eo19 : out std_logic;
eo20 : out std_logic;
eo21 : out std_logic;
eo22 : out std_logic;
eo23 : out std_logic;
eo24 : out std_logic;
eo30 : out std_logic;
eo31 : out std_logic;
-----------------------------------------------------------------
eo3_out : out std_logic;
eo4_out : out std_logic;
q_eo3_out : out std_logic_vector(2 downto 0);
q_eo4_out : out std_logic_vector(2 downto 0);
f_sig_out : out std_logic;
hang_out : out std_logic;
q_hang_out : out std_logic_vector(5 downto 0);
hang2_out : out std_logic;
q_hang2_out : out std_logic_vector(5 downto 0);
-----------------------------------------------------------------
FS_I : out std_logic;
FA_I : out std_logic;
PS1 : out std_logic;
PS0 : out std_logic;
F0 : out std_logic;
F1 : out std_logic;
F2 : out std_logic;
F3 : out std_logic;
---------------------------------------------
AECLKIN : out std_logic;
SIGCLK : out std_logic;
----------------------------------------------
fa_o : in std_logic;
fs_o : in std_logic
);
end a1;
architecture rtl of a1 is
component FIFO is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;
component shift2 IS
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
shiftin : IN STD_LOGIC
);
end component;
component PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC
);
end component;
signal q_count_1 : std_logic_vector(24 downto 0);
signal q_count_2 : std_logic_vector(24 downto 0);
signal q_count_3 : std_logic_vector(24 downto 0);
signal q_gp5 : std_logic_vector(10 downto 0);
signal q_gp7 : std_logic_vector(10 downto 0);
signal clk_10m : std_logic_vector(9 downto 0);
signal filter_clk : std_logic;
signal reset1 : std_logic;
signal read_req1 : std_logic;
signal fifo_dout_1,fifo_dout_2,fifo_dout_3 : std_logic_vector(7 downto 0);
signal uswd : std_logic_vector(11 downto 0);
signal uswd2 : std_logic_vector(11 downto 0);
signal uswd3 : std_logic_vector(11 downto 0);
signal nq_gp7 : std_logic_vector(14 downto 0);
signal r_eo4 : std_logic; ------------------------------------------------------eo4整理后信号
signal q_eo4 : std_logic_vector(2 downto 0);--eo4整理记数期
signal r_eo3 : std_logic; ------------------------------------------------------eo3整理后信号
signal q_eo3 : std_logic_vector(2 downto 0);--eo3整理记数期
signal hang : std_logic;
signal hang2 : std_logic;
signal q_hang : std_logic_vector(5 downto 0);
signal q_hang2 : std_logic_vector(5 downto 0);
signal int5_div : std_logic_vector(2 downto 0);
signal f_sig : std_logic;
begin
U1 : FIFO
port map
(
aclr =>hang,
data => AD2_D(11 downto 4),
rdclk =>AD2_DCO ,
rdreq =>f_sig,
wrclk =>q_gp5(0),
wrreq =>not hang,
q => fifo_dout_3,
rdempty => eo22,
wrfull => eo21,
wrusedw=>uswd
);
U5 : FIFO
port map
(
aclr =>'0',
data => fifo_dout_3,
rdclk =>TEBCLK ,
rdreq =>(not TBBRE)and (not TBCE1),
wrclk =>AD2_DCO,
wrreq =>f_sig ,
-- q => fifo_dout_1,
q => fifo_dout_2,
rdempty => eo23,
wrfull => eo24,
wrusedw=>uswd2
);
U2 : FIFO ------输出fifo
port map
(
aclr =>not gpio9,
data => TEAD(7 downto 0),
rdclk =>eo14 ,---q_gp5(3)模拟eo14
rdreq =>'1',
wrclk =>(not TAAWE)and (not TCE1),---写时钟
wrreq =>'1',
q => fifo_dout_1,
rdempty => eo30,
wrfull => eo31,
wrusedw=>uswd3
);
U3 : PLL
port map
(
inclk0 => clk,
c0 => AECLKIN,
c1 => SIGCLK,
c2 => filter_clk
);
U4 : shift2
port map
(
clock => filter_clk,
q => q_eo3,
shiftin => eo3
);
-- process(clk,q_hang,q_gp5(10)) --中断
-- begin
-- if q_gp5(10)= '0' then
-- q_hang<="000000";
-- elsif q_gp5(10)= '1' then
-- if clk'event and clk= '1' then
-- if q_hang>=20 then
-- q_hang<="010100";
-- else
-- q_hang <= q_hang+ '1';
-- end if;
-- end if;
-- end if;
-- end process;
-- process(q_hang,q_gp5(10))
-- begin
-- if q_gp5(10) = '0' then
-- hang <= '0';
-- elsif q_hang < 20 then
-- hang <= '1';
-- else
-- hang <= '0';
-- end if;
-- end process;
-- process(AD2_DCO,hang,nq_gp7) --中断
-- begin
-- if AD2_DCO'event and AD2_DCO= '0' then
-- if hang = '1' then
-- nq_gp7<="00000000000";
-- else
-- nq_gp7 <= nq_gp7+ '1';
-- end if;
-- end if;
-- end process;
process(clk,q_hang,r_eo4) --中断
begin
if r_eo4= '0' then
q_hang<="000000";
elsif r_eo4= '1' then
if clk'event and clk= '1' then
if q_hang>=5 then
q_hang<="000101";
else
q_hang <= q_hang+ '1';
end if;
end if;
end if;
end process;
process(clk,q_hang2,r_eo3) --中断
begin
if r_eo3= '0' then
q_hang2<="000000";
elsif r_eo3= '1' then
if clk'event and clk= '1' then
if q_hang2>=5 then
q_hang2<="000101";
else
q_hang2 <= q_hang2+ '1';
end if;
end if;
end if;
end process;
process(hang,r_eo4) ----------------r_eo4,eo4整理后信号
begin
if r_eo4 = '0' then
hang <= '0';
elsif q_hang < 5 then
hang <= '1';
else
hang <= '0';
end if;
end process;
process(hang2,r_eo3) ---------------r_eo3,eo3整理后信号
begin
if r_eo3 = '0' then
hang2 <= '0';
elsif q_hang2 < 5 then
hang2 <= '1';
else
hang2 <= '0';
end if;
end process;
process(AD2_DCO,hang,nq_gp7) --中断
begin --------------------nq_gp7 :std_logic_vector(14 downto 0);
if AD2_DCO'event and AD2_DCO= '0' then --------------FIFO,U1
if hang = '1' then
nq_gp7<="000000000000000";
else
nq_gp7 <= nq_gp7+ '1';
end if;
end if;
end process;
process(AD2_DCO,reset,q_gp5) --中断
begin ------------q_gp5 :std_logic_vector(10 downto 0);
if reset = '0' then
q_gp5<="00000000000";
elsif AD2_DCO'event and AD2_DCO= '0' then
q_gp5 <= q_gp5+ '1';
end if;
-- if q_gp5>=1280 then ----------------每640产生中断
-- q_gp5<="00000000000";
-- end if;
end process;
-- process(nq_gp7) ------------------读数据
process(f_sig,q_hang) -----------束信号后产生fifo通信，nq_gp7 通信
begin
-- if nq_gp7 >600 and nq_gp7 <1113 then --------------nq_gp7 :std_logic_vector(14 downto 0);
if nq_gp7 >2890 and nq_gp7 <5451 then
f_sig <= '1';
else
f_sig <= '0';
end if;
end process;
process(clk,reset,q_eo4) --中断
begin
if reset = '0' then
q_eo4<="000";
elsif clk'event and clk= '0' then
q_eo4(0)<=eo4;
q_eo4(1)<=q_eo4(0);
q_eo4(2)<=q_eo4(1);
end if;
end process;
TEBD(7 downto 0) <= fifo_dout_2 when (TBBRE = '0' and TBCE1='0') else -----数据传给DSP
(others => 'Z');
----------------------------------------------------------
EMIFB_OE <= TBCE1;
EMIFB_DIR <= not TBBRE;
EMIFA_OE <= TCE1;
EMIFA_DIR <= not TAARE;
ad_clk<=clk;
-----------------------------------------------------------
-- gpio5<=not hang;--数据中断
gpio5<=not r_eo4; ------------------------数据中断
gpio6<=r_eo3; ------------------------帧同步
gpio7<=r_eo4; ------------------------束同步
gpio11<=gpio10; --新帧
gpio12<=r_eo4;
eo5<=fifo_dout_1(0); -----------------------------------输出数据
eo6<=fifo_dout_1(1);
eo7<=fifo_dout_1(2);
eo8<=fifo_dout_1(3);
eo9<=fifo_dout_1(4);
eo10<=fifo_dout_1(5);
eo11<=fifo_dout_1(6);
eo12<=fifo_dout_1(7);
--------------------
r_eo4<=not(((not q_eo4(0))and (q_eo4(1)) and (q_eo4(2)))or((q_eo4(0))and (not q_eo4(1))and (q_eo4(2)))or((q_eo4(0))and (q_eo4(1))and (not q_eo4(2))) or ((q_eo4(0))and (q_eo4(1))and (q_eo4(2))));
r_eo3<=((not q_eo3(0))and (q_eo3(1)) and (q_eo3(2)))or((q_eo3(0))and (not q_eo3(1))and (q_eo3(2)))or((q_eo3(0))and (q_eo3(1))and (not q_eo3(2))) or ((q_eo3(0))and (q_eo3(1))and (q_eo3(2)));
--------------------
eo3_out<=r_eo3;
eo4_out<=r_eo4;
q_eo3_out<=q_eo3;
q_eo4_out<=q_eo4;
hang_out<=hang;
q_hang_out<=q_hang;
hang2_out<=hang2;
q_hang2_out<=q_hang2;
end rtl;
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