t_div5.vhd

来自「实现60进制的计数」· VHDL 代码 · 共 26 行

--t_div5
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity t_div5 is
 port(clk:in std_logic;
      q:out std_logic);
end t_div5;
architecture rtl of t_div5 is
 signal s:std_logic_vector(2 downto 0):="000";
 signal q1:std_logic;
 begin
process(clk)
 begin
  if clk'event and clk='1' then
     if s="100" then
    s<="000";
   q1<='1';
   else 
     s<=s+'1';
    q1<='0';
     end if;
  end if;
end process;
   q<=q1;
end rtl;