t_counter60.vhd

来自「实现60进制的计数」· VHDL 代码 · 共 48 行

--t_counter60
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity t_counter60 is
port(clk:in std_logic;
     bcd10,bcd1: buffer std_logic_vector(3 downto 0);
     preset:in std_logic;
     co: out std_logic);
end t_counter60;
architecture rtl of t_counter60 is
  signal co_1:std_logic;
  begin
   process(clk,preset)
    begin
     if preset='0' then
      bcd1<="0000";
     else
      if clk='1' and clk'event then
         if bcd1="1001" then
           bcd1<="0000";
          else
           bcd1<=bcd1+'1';
          end if;
      end if;
    end if;
end process;
process(clk,preset,bcd1)
   begin
   if preset='0' then
   bcd10<="0000";
   co_1<='0';
    else
     if clk='1' and clk'event then
        if bcd1="1000" and bcd10="0101" then
          co_1<='1';
        elsif bcd1="1001" and bcd10="0101" then
          bcd10<="0000";
          co_1<='0';
        elsif bcd1="1001" then
          bcd10<=bcd10+'1';
          co_1<='0';
end if;
end if;
end if;
end process;
co<=not co_1;
end rtl;